G01R31/2642

Transistor aging monitor circuit for increased stress-based aging compensation precision, and related methods

A stress-based aging monitor circuit includes a reference ring oscillator circuit and a stressed ring oscillator circuit that each include transistors like the transistors in a circuit to be monitored. Transistors in the stressed ring oscillator circuit receive a negative gate to source voltage bias while the reference ring oscillator is protected from stress. To measure performance degradation due to stress-based aging, the switching frequencies of the reference ring oscillator circuit and the stressed ring oscillator circuit are compared. The reference ring oscillator and the stressed ring oscillator include stress-enhanced inverter circuits configured to amplify stress-based aging effects to increase sensitivity to the performance degradation caused by stress-based aging. Increased sensitivity increases the precision (e.g., higher resolution) of a supply voltage guard band adjustment used to compensate for the performance degradation to reduce or avoid overcompensating for the effects of stress-based aging.

Status check for a switch
11346881 · 2022-05-31 · ·

In some examples, a device includes a control circuit configured to deliver driving signals to a switch. The device also includes a testing circuit configured to cause the control circuit to toggle the switch at a first instance and determine a parameter magnitude at the switch at a second instance after toggling the switch at the first instance by at least determining a voltage magnitude at the switch at the second instance. The testing circuit is also configured to cause the control circuit to toggle the switch after the second instance and determine a parameter magnitude at the switch at a third instance after toggling the switch after the second instance. The testing circuit is further configured to generate an output based on the determined parameter magnitudes at the switch at the second and third instances.

DISPLAY PANEL AND REPAIR METHOD THEREOF
20230268458 · 2023-08-24 ·

A display panel is provided with a conductive layer having a conductive connecting line for connecting a light-emitting element. The conductive layer is further provided with a redundant conductive connecting line for connecting a standby light-emitting element. The repair method of the display panel includes: detecting whether the light-emitting element is abnormal; electrically connecting the redundant conductive connecting line with the conductive connecting line when the light-emitting element is abnormal; and connecting the standby light-emitting element to a redundant conductive connecting line to replace the light-emitting element with abnormal function.

METHOD FOR ASSESSING THE THERMAL LOADING OF A CONVERTER
20220146568 · 2022-05-12 · ·

A method for assessing the state of damage of a semiconductor module that is subject to operational loading, in particular a semiconductor module of a drive system converter, that includes at least one semiconductor component arranged on or in a support structure. It is possible not only to estimate a spent service life for the entire semiconductor module, but also to detect unexpected or undesirable loading states and thus a premature reduction of the remaining service life of the semiconductor module. Continuous load assessments are thus possible already during the operation of the semiconductor module and allow interventions to be made in good time.

DIRECTLY IMPINGING PRESSURE MODULATED SPRAY COOLING AND METHODS OF TARGET TEMPERATURE CONTROL

Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate.

METHOD OF MANUFACTURING WAFER
20230261134 · 2023-08-17 ·

A method of manufacturing a wafer includes a wafer preparing step of preparing a wafer including a plurality of semiconductor devices joined to a substrate by respective adhesive layers, a determining step of determining whether each of the semiconductor devices joined to the substrate is defective or non-defective, a laser beam applying step of applying a laser beam to heat one of the adhesive layers by which one of the semiconductor devices that has been determined as defective is bonded to the substrate, thereby melting the adhesive layer in an area of the wafer that is irradiated with the laser beam, and a treating step of treating the semiconductor device released from a bonded state due to the adhesive layer being melted in the laser beam applying step.

APPARATUS FOR TESTING ELECTRONIC DEVICES

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

SYSTEM AND METHOD FOR TESTING OPTICAL RECEIVERS

Disclosed are a testing unit, system, and method for testing and predicting failure of optical receivers. The testing unit and system are configured to apply different values of current, voltage, heat stress, and illumination load on the optical receivers during testing. The test methods are designed to check dark current, photo current, forward voltage, and drift over time of these parameters.

Method for testing lifetime of surface state carrier of semiconductor

A method for testing a lifetime of a surface state carrier of a semiconductor, including the following steps, 1) a narrow pulse light source is used to emit a light pulse, and coupled to an interior of a near-field optical probe, and the near-field optical probe produces a photon-generated carrier on a surface of a semiconductor material under test through excitation. 2) The excited photon-generated carrier is concentrated on the surface of the semiconductor material, and recombination is conducted continuously with a surface state as a recombination center. 3) A change in a lattice constant is produced due to an electronic volume effect, a stress wave is produced, and a signal of the stress wave is detected in a high-frequency broadband ultrasonic testing mode. 4) Fitting calculation is conducted on the signal of the stress wave to obtain the lifetime of the surface state carrier τ.sub.c.

RELIABILITY EVALUATION METHOD AND SYSTEM OF MICROGRID INVERTER IGBT BASED ON SEGMENTED LSTM
20220120807 · 2022-04-21 · ·

A reliability evaluation method and system for a microgrid inverter IGBT based on segmented long short-term memory (LSTM) is disclosed, including steps as follows. An electrothermal coupling model is constructed to obtain real-time junction temperature data. The original LSTM algorithm is improved to obtain a segmented LSTM prediction network for the aging characteristics of the IGBT. The monitoring value of the IGBT aging parameter is used to perform segmented LSTM prediction to obtain the predicted aging process, and the threshold values of different aging stages are categorized. An aging correction is performed on the aging parameter of the electrothermal coupling model to ensure the accuracy of the junction temperature data. Rainflow-counting algorithm is used to calculate real-time thermal stress load distribution of the IGBT. The fatigue damage theory and the Lesit life prediction model are combined to calculate the real-time cumulative damage and predicted life of the IGBT.