A detector for determining a faulty semiconductor component including a semiconductor component, a contact-via chain, which is situated laterally at a distance from the semiconductor component and which surrounds the semiconductor component in regions, a guard ring, which is situated laterally at a distance from the semiconductor component, and an evaluation unit, which is situated on the semiconductor component, wherein the evaluation unit is designed to apply an electrical voltage to the contact-via chain, in particular a permanent electrical voltage, to detect a resistance value of the contact-via chain and to produce an output signal when the resistance value of the contact-via chain exceeds a threshold value.

A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.

Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

The present invention relates to a test socket heating module and a device test apparatus including the same, and more particularly, to a test socket heating module for performing a high-temperature test on a device, and a device test apparatus including the same. The present invention discloses a test socket heating module (200) including: a support plate (210) installed to be spaced apart a distance from a bottom surface of a test board (100) which is provided with one or more test sockets (20) for performing a test on a device (10) mounted on the test sockets; and one or more heater units (220) which are coupled to the support plate (210) between the test board (100) and the support plate (210), and heat the corresponding test sockets (20), respectively.

A display panel includes a display region including a data line and a pixel that is electrically connected to the data line, a non-display region including a lighting test line that is arranged alternately in a first layer and in a second layer disposed on the first layer, the non-display region being adjacent to the display region and including, and a lighting test unit providing a lighting test voltage to the display region through the lighting test line.

A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including: a first superlattice epitaxial structure, a first GaN based thick layer disposed on the first superlattice epitaxial structure, a second superlattice epitaxial structure disposed on the first GaN based thick layer, and a second GaN based thick layer disposed on the second superlattice epitaxial structure; a channel layer disposed on the buffer structure; a barrier layer disposed on the channel layer; and a two dimensional electron gas layer disposed near an interface between the channel layer and the barrier layer, wherein the total thickness of the first GaN based thick layer and the second GaN based thick layer is more than 2 micrometers.

A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.

Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.