An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

An adaptive body biasing system for silicon on insulator semiconductor devices includes at least one biased logic domain; at least one adaptive body bias generator for generating variable bias voltage; at least one test pad for accessing the generated bias voltage generated by the at least one adaptive body bias generator; and at least one bias switch cell connecting the at least one adaptive body bias generator to the at least one test pad. The at least one bias switch cell is in high-resistive off state during normal operation of the semiconductor device and can be switched to low-resistive on state during test operation. The at least one adaptive body bias generator is connected to the at least one biased logic domain.

A ring oscillator includes a plurality of inverters. A closed loop structure is formed by cascading the inverters. The inverter includes at least one sensitive inverter with a diode-connected transistor. A variation in an MOSFET (Metal Oxide Semiconductor

Field Effect Transistor) threshold voltage of the ring oscillator is detected by analyzing the oscillation frequency of the ring oscillator.

An apparatus includes three components. The first component includes a first transmission line; the second component is coupled with the first component and includes a second transmission line; and the third component electrically coupled with the first component and/or the second component. The transmission lines each include a substrate with a p-well or n-well within the substrate and a shielding layer over the p-well or n-well. The transmission lines also each include a plurality of intermediate conducting layers over the shielding layer, the plurality of intermediate conducting layers coupled by a plurality of vias. The transmission lines further each include a top conducting layer over the plurality of intermediate conducting layers.

A semiconductor circuit having a test function includes: a first circuit block including a circuit for performing a main function of the semiconductor circuit; a first power control block for controlling supply of power to the first circuit block; a second circuit block including a circuit for performing a function of testing the semiconductor circuit; and a second power control block for controlling supply of power to the second circuit block. The semiconductor circuit is operable in a first power mode in which a first pad is supplied with a supply voltage and a second pad is grounded, or in a second power mode in which the second pad is supplied with the supply voltage and the first pad is grounded. The second power control block is implemented as a diode.

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level.

A micro-electro-mechanical device includes a movable structure. The movable structure includes a test structure changing an electrical characteristic, if the movable structure is damaged. Further, a method for detecting damaging of a micro-electro-mechanical device includes detecting a change of an electrical characteristic of the electrical test structure of the movable structure. Further, the method includes indicating a deviation of the electrical characteristic from a predefined tolerable range.

A semiconductor device includes first and second contact parts that are disposed close to each other with an interval therebetween and form a screw hole (connection area) to which an external connection terminal is connected. The first contact part extends from a side of a case via a first linkage part that extends from the side, and the second contact part extends from the side via a second linkage part that extends from the side. The first and second linkage parts are disposed away from each other by at least a certain interval. In this way, the semiconductor device is allowed to have first and second semiconductor chips connected in parallel with each other and function as a semiconductor device. In addition, electrical characteristics of the first and second semiconductor chips of the semiconductor device are individually measured.

The present disclosure provides test structures, fabrication methods thereof and test methods thereof. An exemplary test structure includes a substrate having a to-be-tested region having at least one fin and a peripheral region having at least one fin surrounding the to-be-tested region; an insulation layer covering portions of side surfaces of the fins; at least one first gate structure covering side and top surfaces of the fin in the to-be-tested region; second gate structures covering side and top surfaces of the fins in the peripheral region; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the first gate structure and adjacent second gate structures; and a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region. The plurality of first conductive structures cross over and are on source/drain regions of at least two fins.