A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.

A display panel includes a display region including a data line and a pixel that is electrically connected to the data line, a non-display region including a lighting test line that is arranged alternately in a first layer and in a second layer disposed on the first layer, the non-display region being adjacent to the display region and including, and a lighting test unit providing a lighting test voltage to the display region through the lighting test line.

A semiconductor circuit having a test function is operated by applying power between a first pad and a second pad, and includes a first circuit block including a circuit for performing a main function of the semiconductor circuit; a second circuit block including a circuit for performing a function of testing the semiconductor circuit; and a diode connected in series with the second circuit block. In accordance with the semiconductor circuit having a test function, additional control pads and control signals are not required, thus suppressing an increase in the area of a semiconductor chip due to pads by reducing the number of pads.

A semiconductor package includes a semiconductor die, an antenna embedded in insulating material contacting a first main side of the semiconductor die and electrically connected to a first pad of the semiconductor die and a coupling structure embedded in the insulating material, electrically connected to a second pad of the semiconductor die and spaced from the antenna. The coupling structure is configured to sense energy radiated from the antenna or a feedline connected to the antenna. The semiconductor die includes a transmitter circuit operable to drive a signal onto the antenna through the feedline. The semiconductor die also includes a transmit path verification circuit operable to indicate if the antenna is electrically connected to the first pad of the semiconductor die based on a signal from the coupling structure that corresponds to the energy sensed by the coupling structure.

A method for inspecting a light-emitting diode package is provided. The inspecting method comprises the following steps. First, provide a light-emitting diode package, wherein the light-emitting diode package includes a light-emitting diode chip, a lead frame and an encapsulation body. The light-emitting diode chip is disposed on the lead frame and the height of the lead frame is higher than that of the light-emitting diode chip. The encapsulation body covers the light-emitting diode chip and a portion of the lead frame. Next, remove a portion of the encapsulation body to expose the upper surface of the light-emitting diode chip.

Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

Provided is a testing method for testing a semiconductor device provided with a main element portion including a main transistor portion and a main diode portion, and a sensing transistor portion for current detection, the testing method having: operating an element by causing a diode operation of the sensing transistor portion in the semiconductor device in a chip or wafer state; measuring the element by measuring a voltage-current characteristic showing a relationship between a voltage between main terminals of the sensing transistor portion and a current flowing through the main terminals during the diode operation; and determining the element by determining a defectiveness of the semiconductor device based on the voltage-current characteristic.

Main cells that constitute a semiconductor element having a trench gate structure include first cells, and second cells having a structure in which gate insulating films are more easily broken by energization than those in the first cells, and the number of which is smaller than that of the first cells. At a time of driving the semiconductor element, a common gate drive voltage is applied to gate electrodes of the first cells and the second cells. An electrical characteristic is measured to detect failure of the second cells due to energization at the time of driving. The gate electrodes of the failed second cells are electrically isolated from the gate electrodes of the first cells so that the gate drive voltage is not applied to the failed second cells. The failure of the first cells is predicted based on the failure of the second cells.

This document describes systems and techniques directed at semiconductor fault detection. In aspects, a semiconductor device includes a physical structure that facilitates detection and localization of defects. The physical structure includes at least one conductive interconnect that extends through two or more layers of a semiconductor device, enabling an electrical detection of faults. Such systems and techniques can help improve yield, accelerate failure analysis debugging, and improve reliability of semiconductor devices.

Provided is a technique for enhancing the accuracy of deterioration diagnosis in a semiconductor device. The semiconductor device relating to the technique disclosed in the present specification is provided with a case, a semiconductor chip inside the case, a metal wire bonded to an upper surface of the semiconductor chip, at least one test piece inside the case, and a pair of terminals provided outside the case and connected to the test piece. The test piece is separated from the metal wire inside the case.