A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.

Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.

A method of testing a semiconductor device may include preparing a semiconductor substrate in which the semiconductor substrate includes a test element group including first and second test circuits, measuring first and second leakage currents in the first and second test circuits, respectively, and calculating leakage components by comparing the first and second leakage currents. Each of the first and second test circuits may include an active region, which is an upper portion of the semiconductor substrate, a gate electrode, which is configured to cross the active region and to extend in a first direction, and an active contact, which is on the active region, is spaced apart from the gate electrode, and extends in the first direction. The second test circuit may further include a first gate contact that is connected to the gate electrode and overlaps the active region in a vertical direction perpendicular to the substrate.

A device comprising at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

A failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method includes the steps of: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array. The positioning method helps to improve the yield of semiconductor device based on the above defect adjustment process.

A dummy element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a first resistive layer deposited on the lower insulating film; an interlayer insulating film covering the first resistive layer; a first pad-forming electrode deposited on the interlayer insulating film so as to be connected to the first resistive layer, and including an extending portion to be in Schottky contact with the semiconductor substrate; a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact; and a counter electrode allocated under the semiconductor substrate, the dummy element simulating a defective state in the lower insulating film and the interlayer insulating film immediately under the first pad-forming electrode included in a corresponding resistive element as a target to be examined.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

Reference center circuitry for a metrology system is disclosed. In one embodiment, the circuitry includes a reference sensor having a topology and characteristics identical to a number of sensors throughout an IC. The both the reference sensor and the sensors on the IC may be used to perform voltage and temperature measurements. The reference sensor may receive a voltage from a precision voltage supply, and may be used as a sensor to provide a basis for calibrating the other sensors, as well. Thereafter, temperature readings obtained from the other sensors may be correlated to the readings obtained by the reference sensor for enhanced accuracy. The reference center circuitry also includes analog process monitoring circuitry, which may be coupled to some, if not all of the transistors implemented on an IC.

A semiconductor chip and a circuit and a method for electrically testing a semiconductor chip are disclosed, which pertain to the field of semiconductor technology. The semiconductor chip includes: a first electrical connection point, configured to connect a first pole of a force power supply in a Kelvin testing circuit; and a second electrical connection point, configured to connect a first terminal of a detecting device in the Kelvin testing circuit, wherein the first electrical connection point and the second electrical connection point are connected with each other within the semiconductor chip, and the first pole of the force power supply and the first terminal of the detecting device are arranged on the same side of the Kelvin testing circuit. According to the present disclosure, the semiconductor chip can be electrically tested with an enhanced accuracy and no impact from external contact and conduction resistances.

A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.