A semiconductor device including a substrate including a bonding pad region and an edge region; and a residual test pattern on the edge region of the substrate, wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate.

Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.

A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.

A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layerthe first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second average Al composition ratio of the second superlattice epitaxial structure.

Reference center circuitry for a metrology system is disclosed. In one embodiment, the circuitry includes a reference sensor having a topology and characteristics identical to a number of sensors throughout an IC. The both the reference sensor and the sensors on the IC may be used to perform voltage and temperature measurements. The reference sensor may receive a voltage from a precision voltage supply, and may be used as a sensor to provide a basis for calibrating the other sensors, as well. Thereafter, temperature readings obtained from the other sensors may be correlated to the readings obtained by the reference sensor for enhanced accuracy. The reference center circuitry also includes analog process monitoring circuitry, which may be coupled to some, if not all of the transistors implemented on an IC.

A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

A self-healing microchip comprising a commercial-off-the-shelf (COTS) microchip lacking radiation shielding. The self-healing microchip includes one or more microheaters that are integrated directly upon a surface of the COTS microchip, a self-test circuit which detects a degradation in the COTS microchip, and one or more temperature sensors. The one or more microheaters may be formed directly upon a backside surface of the COTS microchip using tungsten sputtered shadow mask patterning or by lithography and etching, for example. In response to a detected degradation in the COTS microchip, a temperature control configures an output temperature generated by the one or more microheaters and an amount of time at which the output temperature is maintained to cause annealing in the microchip responsive to the detected degradation in the COTS microchip.

The present invention provides a failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method comprises: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method provided by the present invention, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array. The positioning method helps to improve the yield of semiconductor device based on the above defect adjustment process.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.