G01R31/265

Analysis of electro-optic waveforms

An optic probe is used to measure signals from a device under test. The optic probe is positioned at a target probe location within a cell of the device under test, the cell including a target net to be measured and a plurality of non-target nets. A test pattern is applied to the cell with the optic probe a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: (i) simulating a combinational logic analysis (CLA) cross-talk waveform to model cross-talk from selected non-target nets by simulating an optical response of the cell to the test pattern with the target net masked; (ii) estimating a cross-talk weight; and (iii) determining a target net waveform by weighting the CLA cross-talk waveform according to the cross-talk weight and subtracting the weighted CLA cross-talk waveform from the LP waveform.

Metrology apparatus and method for determining a characteristic of one or more structures on a substrate

Disclosed is a method for obtaining a computationally determined interference electric field describing scattering of radiation by a pair of structures comprising a first structure and a second structure on a substrate. The method comprises determining a first electric field relating to first radiation scattered by the first structure; determining a second electric field relating to second radiation scattered by the second structure; and computationally determining the interference of the first electric field and second electric field, to obtain a computationally determined interference electric field.

DUAL-SIDED WAFER IMAGING APPARATUS AND METHODS THEREOF
20210223308 · 2021-07-22 ·

The present disclosure provides a dual-sided wafer imaging apparatus and methods thereof. The dual-sided wafer imaging apparatus includes one or more load ports, one or more mechanical arms for transporting a wafer, a wafer transfer stage, a first line scan camera mounted below the wafer transfer stage, a second line scan camera mounted above the wafer transfer stage, a first optical lens mounted on the first line scan camera, a second optical lens mounted on the second line scan camera, and line light sources respectively mounted below and above the wafer transfer stage. The load ports are configured for an automated load operation or unload operation of a wafer pod of an automated transport equipment. The wafer transfer stage includes vacuum suction points in contact with a backside of the wafer, and the wafer transfer stage further includes a drive motor producing a linear reciprocating motion for moving the wafer.

DEVICE AND METHOD FOR MONITORING POWER SEMICONDUCTOR DIE

A device comprising at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

Light emitting diode (LED) test apparatus and method of manufacture
11037841 · 2021-06-15 · ·

Embodiments relate to functional test methods useful for fabricating products containing Light Emitting Diode (LED) structures. In particular, LED arrays are functionally tested by injecting current via a displacement current coupling device using a field plate comprising of an electrode and insulator placed in close proximity to the LED array. A controlled voltage waveform is then applied to the field plate electrode to excite the LED devices in parallel for high-throughput. A camera records the individual light emission resulting from the electrical excitation to yield a function test of a plurality of LED devices. Changing the voltage conditions can excite the LEDs at differing current density levels to functionally measure external quantum efficiency and other important device functional parameters.

METHOD OF ANALYZING SEMICONDUCTOR STRUCTURE
20210172995 · 2021-06-10 ·

A method includes providing a detector disposed above a semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector; rotating the stage; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.

Method for calibrating verticality of particle beam and system applied to semiconductor fabrication process

The present invention provides a method for calibrating verticality of a particle beam. The method includes: providing a baseplate having a first sensor and a second sensor; emitting the particle beam to the first sensor of the baseplate from an emitter, such that a first datum is collected when the first sensor receives the particle beam; emitting the particle beam to the second sensor of the baseplate from the emitter, such that a second datum is collected when the second sensor receives the particle beam; calculating a first calibrating datum based on the first datum and the second datum; and adjusting the baseplate or the emitter based on the first calibrating datum if the first calibrating datum is out of a first predetermined range.

Electro-optic waveform analysis process

A reconfigurable optic probe is used to measure signals from a device under test. The reconfigurable optic probe is positioned at a target probe location within a cell of the device under test. The cell including a target net to be measured and non-target nets. A test pattern is applied to the cell and a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: i) configuring the reconfigurable optic probe to produce a ring-shaped beam having a relatively low-intensity region central to the ring-shaped beam; (ii) re-applying the test pattern to the cell at the target probe location with the relatively low-intensity region applied to the target net and obtaining a cross-talk LP waveform in response; (iii) normalizing the cross-talk LP waveform; and (iv) determining a target net waveform by subtracting the normalized cross-talk LP waveform from the LP waveform.

System and method of preparing integrated circuits for backside probing using charged particle beams

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.

System and method of preparing integrated circuits for backside probing using charged particle beams

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.