Patent classifications
G01R31/265
APPARATUS AND METHOD OF INCREASING PRECISION CONTROL OF CHARGE DEPOSITION ONTO A SEMICONDUCTOR WAFER SUBSTRATE
The present invention relates to corona charge deposition systems that use High Voltage (HV) amplifiers for precisely controlling corona charge deposition. Some implementations, provide a corona charge deposition system that uses multiple voltage sources to maintain specified voltages applied on several electrodes to precisely control the corona current required to deposit a desired amount of charge on a sample. The HV amplifiers are able to source and sink currents to maintain stable voltages applied on control electrodes in the presence of a higher voltage applied on a needle electrode. The proposed apparatus and method of monitoring multiple signals, controlling multiple voltages, and predicting charge profile deposited on a sample can precisely control charge deposition processes.
METHOD AND APPARATUS FOR NON-INVASIVE, NON-INTRUSIVE, AND UN-GROUNDED, SIMULTANEOUS CORONA DEPOSITION AND SHG MEASUREMENTS
Apparatus is described for performing simultaneous corona deposition and surface electric field induced second harmonic (EFISH) measurements. Example designs include systems including corona guns having a focus tube for deposition of corona charge with windows therein for passage of a laser beam incident on and reflected from a sample surface. Various designs may also employ masks proximal the distal end of the focusing tube and/or proximal the sample surface. In some implementations, the apparatus is used to make ungrounded and therefore non-invasive measurements, for example, on dielectric on semiconductor such as, e.g., interface state density (D.sub.it), flatband voltage (V.sub.fb) and/or lifetime measurements.
Inspection apparatus and inspection method
This inspection apparatus is for inspecting an inspection subject device. The inspection subject device is formed on an object to be inspected, and is a reverse-side irradiation-type imaging device into which light enters from the reverse side opposite to the side where a wiring layer is provided. This inspection apparatus has: a placement table having a transparent surface on which the object to be inspected is placed; a light irradiation mechanism that is provided in the placement table and that irradiates the to-be-inspected object placed on the placement table with light through the placement surface; and an acquisition unit that acquires in-plane distribution of illuminance of light from the placement table.
Semiconductor wafer evaluation apparatus and semiconductor wafer manufacturing method
A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.
Test structure and test method for online detection of metal via open circuit
The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.
MULTIPLEXED DLTS AND HSCV MEASUREMENT SYSTEM
Techniques and systems are described that enable multiplexed DLTS and HSCV measurements.
MULTIPLEXED DLTS AND HSCV MEASUREMENT SYSTEM
Techniques and systems are described that enable multiplexed DLTS and HSCV measurements.
Methods for inspecting semiconductor wafers
Methods and systems are presented for analysing semiconductor materials as they progress along a production line, using photoluminescence images acquired using line-scanning techniques. The photoluminescence images can be analysed to obtain spatially resolved information on one or more properties of said material, such as lateral charge carrier transport, defects and the presence of cracks. In one preferred embodiment the methods and systems are used to obtain series resistance images of silicon photovoltaic cells without making electrical contact with the sample cell.
Method of analyzing semiconductor structure
A method includes providing a detector disposed above a semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector; rotating the stage; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.
SYSTEMS AND METHODS USING STROBOSCOPIC UNIVERSAL STRUCTURE-ENERGY FLOW CORRELATION SCATTERING MICROSCOPY
The disclosure provides for systems and methods which utilize an optical scattering microscope with a spatiotemporal approach to measure the nature and extent of energy flow across electronic or semiconductor materials.