G01R31/265

Detection Method for Sensitive Parts of Ionization Damage in Bipolar Transistor

The present invention provides a detection method for sensitive parts of ionization damage in a bipolar transistor, which includes the following steps: selecting an irradiation source, and carrying out irradiation test on the bipolar transistor to be tested; installing the irradiated bipolar transistor on a test bench of a deep level transient spectroscopy system, and setting test parameters; selecting at least two different bias voltages, and testing the bipolar transistor to obtain a deep level transient spectrum; determining whether a defect is an ionization defect according to a peak position of the defect signal in the deep level transient spectrum; determining the defect type as oxidation trapped charges or an interface state according to the level of the defect signal in the deep level transient spectrum; and determining the sensitive area of ionization damage in the bipolar transistor according to the determination result of the defect signal type.

In-line device electrical property estimating method and test structure of the same

A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.

System and method of preparing integrated circuits for backside probing using charged particle beams

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.

System and method of preparing integrated circuits for backside probing using charged particle beams

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.

SEMICONDUCTOR FAULT ANALYSIS DEVICE AND SEMICONDUCTOR FAULT ANALYSIS METHOD
20230061399 · 2023-03-02 · ·

A control part of a semiconductor fault analysis device outputs an alignment command that moves a chuck to a position at which a target is detectable by a first optical detection part and then aligns an optical axis of a second optical system with an optical axis of a first optical system with the target as a reference, and outputs an analysis command that applies a stimulus signal to a semiconductor device and receives light from the semiconductor device emitted according to a stimulus signal with at least one of a first optical detection part and a second optical detection part in a state in which a positional relationship between the optical axis of the first optical system and the optical axis of the second optical system is maintained.

ANALYSIS METHOD, STORAGE MEDIUM, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
20230118297 · 2023-04-20 ·

Provided is an analysis method including acquiring measurement values of a characteristic of a plurality of semiconductor devices of a measurement group in which a concentration of a first impurity and an irradiation amount of a charged particle beam are included in a set range, generating a measurement distribution showing a distribution, in the measurement group, of the measurement values of the characteristic, generating a virtual distribution in which samples of the characteristic are distributed in a range that is wider than the measurement distribution by simulating, based on the measurement distribution, the characteristic of a plurality of the semiconductor devices that is virtual, and calculating a defect rate in the virtual distribution.

ANALYSIS METHOD, STORAGE MEDIUM, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
20230118297 · 2023-04-20 ·

Provided is an analysis method including acquiring measurement values of a characteristic of a plurality of semiconductor devices of a measurement group in which a concentration of a first impurity and an irradiation amount of a charged particle beam are included in a set range, generating a measurement distribution showing a distribution, in the measurement group, of the measurement values of the characteristic, generating a virtual distribution in which samples of the characteristic are distributed in a range that is wider than the measurement distribution by simulating, based on the measurement distribution, the characteristic of a plurality of the semiconductor devices that is virtual, and calculating a defect rate in the virtual distribution.

Test Structure and Test Method for Online Detection of Metal Via Open Circuit

The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

Group III nitride semiconductor substrate
11662374 · 2023-05-30 · ·

According to the present invention, there is provided a group III nitride semiconductor substrate (free-standing substrate 30) that is formed of group III nitride semiconductor crystals. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A variation coefficient of an emission wavelength of each of the first and second main surfaces, which is calculated by dividing a standard deviation of an emission wavelength by an average value of the emission wavelength, is 0.05% or less in photoluminescence (PL) measurement in which mapping is performed in units of an area of 1 mm.sup.2 by emitting helium-cadmium (He—Cd) laser, which has a wavelength of 325 nm and an output of 10 mW or more and 40 mW or less, at room temperature. In a case where devices are manufactured over the free-standing substrate 30, variations in quality among the devices are suppressed.

Test circuit and method

A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.