A method to establish a degradation state of electrical connections in a power semiconductor device comprising: measuring at least two voltage drop values under two respective current values for the same temperature value. The two current values are strictly different or the measurements are made under two distinct gate levels of a transistor; saving the measured values as calibration data; monitoring operational conditions of said power semiconductor device; measuring at least two voltage drop values under respective same current values as preceding, and at two respective moments during which the monitored operational conditions corresponding to two respective predefined sets of criteria related to states of operation and to a common temperature; saving the at least two values as operational data; calculating a numerical index in a manner to estimate a degradation state of said power semiconductor device.

A method to establish a degradation state of electrical connections in a power semiconductor device comprising: measuring at least two voltage drop values under two respective current values for the same temperature value. The two current values are strictly different or the measurements are made under two distinct gate levels of a transistor; saving the measured values as calibration data; monitoring operational conditions of said power semiconductor device; measuring at least two voltage drop values under respective same current values as preceding, and at two respective moments during which the monitored operational conditions corresponding to two respective predefined sets of criteria related to states of operation and to a common temperature; saving the at least two values as operational data; calculating a numerical index in a manner to estimate a degradation state of said power semiconductor device.

A test method and device for a contact resistor are provided, configured to test a contact resistor of a metal-oxide-semiconductor (MOS) transistor. The method includes: a resistance value per area and a temperature coefficient of resistance of the contact resistor are acquired; and a target resistance value of the contact resistor is determined according to the resistance value per area, the temperature coefficient of resistance, and an area of the contact resistor.

A conduction inspection jig includes a first member having first openings, a second member having second openings and formed to be positioned above the first member, a third member formed to be positioned between the first member and the second member such that the third member forms a space between the first member and the second member and at least substantially surrounds the space, and a probe formed to pass through one of the first openings and one of the second openings such that the probe extends through the space formed between the first member and the second member.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

A test apparatus comprising a tester interface board (TIB) affixed in a slot of a tester rack, wherein the TIB comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT). The test apparatus further comprises a carrier comprising an array of DUTs, wherein the carrier is operable to slide into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket on the TIB. Further, the test apparatus comprises a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier.

Circuitry for testing an integrated capacitor that includes a first capacitor, a supply node for connecting to a voltage supply, a test node for connecting to the integrated capacitor, and a charge monitoring circuit. The circuitry is operable in a sequence of states including a first state in which the first capacitor is connected to the supply node and is disconnected from the test node so as to charge the first capacitor to a test voltage and a second state in which the first capacitor is disconnected from the supply node and is connected to the test node to apply the test voltage to the integrated capacitor. The charge monitoring circuit is configured to monitor a charge transfer from the first capacitor to the integrated capacitor in said second state and to generate a measurement value based on an amount of the charge transfer.