An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Circuitry for testing an integrated capacitor that includes a first capacitor, a supply node for connecting to a voltage supply, a test node for connecting to the integrated capacitor, and a charge monitoring circuit. The circuitry is operable in a sequence of states including a first state in which the first capacitor is connected to the supply node and is disconnected from the test node so as to charge the first capacitor to a test voltage and a second state in which the first capacitor is disconnected from the supply node and is connected to the test node to apply the test voltage to the integrated capacitor. The charge monitoring circuit is configured to monitor a charge transfer from the first capacitor to the integrated capacitor in said second state and to generate a measurement value based on an amount of the charge transfer.

A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

The invention is a test system for testing silicon wafers or packaged devices. The system includes a tester having multiple testing stacks that each hold a vertical stack of test engines, data buffers, pin drivers, and other resources, which are electrically connected on one side to a wafer or DUT and on the other side to a test host computer via fast data links. Each testing stack is disposed on a top side of a wafer contactor electrically connected to a wafer or a load board electrically connected to a DUT. The system includes a cooling system to remove heat during operation. The system minimizes the data signal path between the pads of the devices being tested and the pin drivers of the tester, the test engines, and the test host computer. High performance is possible by the connection of bottom of each testing stack directly to the wafer contactor.

Embodiments of the present disclosure provide a method and a device for detecting a threshold voltage drift of a transistor in a pixel circuit, which are used for detecting the threshold voltage drift of the transistor to be detected in the pixel circuit. The transistor to be detected is at least one of the driving transistor and the detection transistor. The detection method comprises: inputting, during an inputting stage, a first turning-on voltage to the second scanning terminal, so as to turn on the detection transistor, enabling writing a first voltage into the second node through the detection signal terminal; inputting, during a detection stage, a first turning-off voltage to the second scanning terminal, so as to turn off the detection transistor, thereby detecting an actual voltage at the second node; and determining a state of the threshold voltage drift of the transistor to be detected according to the actual voltage and the first voltage.

Embodiments of the present disclosure provide a method and a device for detecting a threshold voltage drift of a transistor in a pixel circuit, which are used for detecting the threshold voltage drift of the transistor to be detected in the pixel circuit. The transistor to be detected is at least one of the driving transistor and the detection transistor. The detection method comprises: inputting, during an inputting stage, a first turning-on voltage to the second scanning terminal, so as to turn on the detection transistor, enabling writing a first voltage into the second node through the detection signal terminal; inputting, during a detection stage, a first turning-off voltage to the second scanning terminal, so as to turn off the detection transistor, thereby detecting an actual voltage at the second node; and determining a state of the threshold voltage drift of the transistor to be detected according to the actual voltage and the first voltage.

An LED package structure includes a multilayered circuit board, a plurality of lighting elements, a control unit, a reflecting unit, a package unit, a plurality of test paths and a plurality of operation paths. The multilayered circuit board includes a plurality of testing pads, a first electrical connecting pad and a plurality of second electrical connecting pads. The lighting elements are disposed on the multilayered circuit board. The control unit is electrically connected to the lighting elements. The reflecting unit is disposed on the multilayered circuit board and surrounds the lighting elements. The package unit covers the lighting elements. The test paths are in electrical connection with the first electrical connecting pad, the lighting elements and one of the testing pads. The operation paths are in electrical connection with the first electrical connecting pad, the control unit, the lighting elements and one of the second electrical connecting pads.