Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit and a respective top surface, which extends in a horizontal plane, and are stacked on one another in a vertical direction, transverse to the horizontal plane, and staggered parallel to the same horizontal plane. Provided at a first portion of the top surface is a first plurality of contact pads, and provided at a second portion of the top surface is a second plurality of contact pads. The first portion is covered by a overlying die, and the second portion is exposed and freely accessible. At least some of the contact pads of the first plurality are electrically coupled to internal through silicon vias traversing a substrate of the overlying die to put overlapping dies in electrical contact.

An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit and a respective top surface, which extends in a horizontal plane, and are stacked on one another in a vertical direction, transverse to the horizontal plane, and staggered parallel to the same horizontal plane. Provided at a first portion of the top surface is a first plurality of contact pads, and provided at a second portion of the top surface is a second plurality of contact pads. The first portion is covered by a overlying die, and the second portion is exposed and freely accessible. At least some of the contact pads of the first plurality are electrically coupled to internal through silicon vias traversing a substrate of the overlying die to put overlapping dies in electrical contact.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

A probe card for testing electrical properties of a device under test (DUT) includes a plurality of semiconductor devices, which includes a substrate; and at least one transmission antenna, which is implemented as a chip on film (COF) type and attached to the substrate, wirelessly transmitting at least one of electric power and data to each of the plurality of semiconductor devices.

A probe card for testing electrical properties of a device under test (DUT) includes a plurality of semiconductor devices, which includes a substrate; and at least one transmission antenna, which is implemented as a chip on film (COF) type and attached to the substrate, wirelessly transmitting at least one of electric power and data to each of the plurality of semiconductor devices.

A device for monitoring a power semiconductor switch includes a circuit section for applying to the power semiconductor switch an HF voltage having a frequency above a switching threshold of the power semiconductor switch, a shunt resistor for detecting an actual HF current resulting from application of the HF voltage to the power semiconductor switch, a monitoring circuit for comparing the actual HF current with an expected HF current that depends on a switching state of the power semiconductor switch when the HF voltage is applied to the power semiconductor switch, and a comparator for generating a power semiconductor status signal depending on a result of the comparison. A corresponding method for monitoring a power semiconductor switch of this type is also described.