One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

The present invention is directed to a system for testing printed circuit boards. The system is configured to test the simultaneously test a multiplicity of printed circuit boards. The system examines the electrical characteristics of a printed circuit board and is operable to identify if a printed circuit board meets a desired characteristic.

A system for testing an electronic circuit board test coupon, including a test chamber. The test chamber can have at least one port through which a port extension member holding a test coupon can be inserted, minimizing air flow between the interior space of the test chamber and the surrounding area to adequately maintain elevated heat and humidity conditions within the test chamber.

An electronic device including a printed circuit board has a degradation detection circuit that detects degradation of the printed circuit board at a plurality of different degradation levels, and a warning output unit that outputs a warning in accordance with the degradation level detected by the degradation detection circuit.

A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin having a swaged head electrically connected to the external analyzer.

A semiconductor device includes: a first circuit; a first power switch provided either between a power supply potential terminal and a power supply potential node of the first circuit or between a reference potential terminal and a reference potential node of the first circuit; a power switch control circuit configured to control a voltage of a control terminal of the first power switch; a test terminal; and a first test control circuit configured to control connection of the test terminal and the control terminal of the first power switch.

A test device for testing a flat module includes a test station and a cover movable relative to the test station between a test position and a removal position. At least two holding devices are arranged and formed on the cover in such a way that, when the cover moves from its removal position into the test position, they releasably connect to the flat module arranged in the test station in such a way that, when the cover moves from its test position into the removal position, the flat module is held by the at least two holding devices.

A circuit board structure includes a test terminal. The circuit board structure includes and interface circuit board and a functional circuit board. The interface circuit board includes common test terminals shared by different functional circuit boards. The functional circuit board realizes a product function. The functional circuit board is selected from a plurality of functional circuit boards respectively realizing different product functions. Circuit components required for each product function are mounted on the corresponding functional circuit board.

The present invention is directed to a system for testing printed circuit boards. The system is configured to test the simultaneously test a multiplicity of printed circuit boards. The system examines the electrical characteristics of a printed circuit board and is operable to identify if a printed circuit board meets a desired characteristic.

A method includes characterizing the effects of an electric field on a first set of printed wiring boards (PWBs) by testing the first set of PWBs to generate test data, using the test data to determine a dielectric life curve of the first set of PWBs, and based on the dielectric life curve, defining a screening time and a screening voltage to screen for premature failures in a second set of PWBs due to electric fields.