A measuring instrument for measuring electrical characteristics of a device under test (DUT) includes a signal generator for generating a synchronization signal transmittable to a receiver and a phase shifter. The measuring instrument is configured to receive a retransmission of the synchronization signal from the receiver. The phase shifter configured to receive the synchronization signal from the signal generator and the retransmission of the synchronization signal from the receiver and shift a phase of the synchronization signal so that pulse edges of the synchronization signal are aligned at the measuring instrument and the receiver.

An optical system comprises a number of optics modules, wherein the respective optics module comprises: a number of displaceable optical elements for guiding radiation in the optical system; a number of actuator/sensor devices, wherein at least one of the actuator/sensor devices is assigned to the respective optical element, wherein the respective actuator/sensor device is configured to displace the assigned optical element and/or to acquire a position of the assigned optical element; a vacuum-tight housing; and an electronics unit in the vacuum-tight housing and configured to actuate the respective actuator/sensor device on the basis of received actuation data, wherein the electronics unit has a first electronics region containing a number of electrical and/or electronic component parts and that generates, and a second electronics region containing a number of electrical and/or electronic component parts.

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

A sampling clock testing circuit includes a clock circuit, a processing circuit and a phase determining circuit. The clock circuit generates a clock signal and switches phases of the clock signal according to a horizontal synchronous signal. The processing circuit samples a data signal according to the clock signal with the phases to generate pixel data groups each of which is corresponding to one phase. The phase determining circuit generates calculated values according to the pixel data groups, in which each phase is corresponding to one calculated value. The phase determining circuit selects a specific calculated value from the calculated values according to a predetermined condition, and determines a specific phase corresponding to the specific calculated value. The processing circuit samples a subsequent data signal according to the clock signal switched to the specific phase to generate subsequent pixel data.

An array substrate, and a display panel and a test method therefor are provided. The array substrate includes a plurality of display signal lines disposed in a display area, and a plurality of first pads and a plurality of second pads disposed in a peripheral area around the display area and electrically connected to the respective plurality of display signal lines. A first test area and a second test area are disposed in a first direction on two sides of a primary area respectively. The first pad includes a first primary part and the second pad includes a second primary part. The first primary parts and the second primary parts are disposed in the primary area and are disposed alternately in a second direction.

A measurement instrument for measuring electrical characteristics of a device under test (DUT) includes a synchronization signal generator, a coarse phase detection counter and a fine phase detection counter. The synchronization signal generator is connectable with a receiver via a fiber optic cable and a duplexer configured to transmit a synchronization signal from the measurement instrument to the receiver and retransmit the received synchronization signal from the receiver to the measurement instrument. The coarse phase detection counter and the fine phase detection counter are configured to determine one or both of a distance from the receiver to the measurement instrument and a phase shift in the synchronization signal between the receiver and the measurement instrument.

A measurement instrument for measuring electrical characteristics of a device under test (DUT) includes a synchronization signal generator configured to generate a synchronization signal transmittable from the measurement instrument to a receiver. The synchronization generator comprises a phase-locked loop (PLL) that locks the phase of the LO signal to the synchronization signal. The A/D clock signal is generated from the synchronization signal.

A testing pluggable module includes a pluggable body extending between a front end and a mating end defining a mating interface with a communication connector of a receptacle assembly. The mating end is receivable in a module cavity of the receptacle assembly to mate with the communication connector. The pluggable body has an exterior forward of the mating end. The testing pluggable module includes an internal circuit board held in the pluggable body having a testing circuit operating at least one testing function. The testing pluggable module includes a user interface on the exterior of the pluggable body. The user interface has an input configured to operably control the at least one testing function of the testing circuit.

Various embodiments of the teachings herein include a method for measuring valve characteristic parameters of a valve actuator. An example method includes: resetting the push rod to a top end position; driving the push rod; measuring the DC drive current in real time; recording a first position of the push rod at the start of a first abrupt change in the DC drive current when the first abrupt change in the DC drive current is detected and lasts for more than a first preset time period; continuing to drive the push rod and measure the DC drive current in real time; recording a second position of the push rod at the start of a second abrupt change; and calculating the stroke length of the valve based on the first position and the second position.

According to one aspect, embodiments of the invention provide a wireless device comprising an overstress indicator circuit including a sense circuit configured to monitor a parameter of the wireless device and generate a sense signal corresponding to the parameter, a detection circuit configured to receive the sense signal from the sense circuit and generate a detection signal in response to a determination that the sense signal is indicative of an overstress condition in the device, an interface circuit, and a memory circuit coupled to the detection circuit and the interface circuit and configured to store an overstress condition indication for access via the interface circuit in response to receiving the detection signal, at least one power amplifier coupled to the interface circuit, and a transceiver coupled to the at least one power amplifier and configured to produce an RF transmit signal and to receive an RF receive signal.