Provided is an integrated circuit and a test method for an integrated circuit. The integrated circuit includes at least one first branch and at least one second branch. The first branch includes at least one first capacitor. The first end of the first branch is electrically connected to the first end of the second branch, and the second end of the first branch is not connected to the second end of the second branch, to conduct a low-frequency test. The low-frequency test includes application of a low-frequency test signal between the first end of the first branch and the second end of the first branch to test the first branch.

A test array structure includes a substrate, first and second cells, first and second bit-line rings and four word-lines. Each of the first and second cells has a first drain region, a first gate region, a source region, a second gate region and a second drain region connected together in sequence. The first drain region and the first gate region of the first cell are located within the first bit-line ring. The second drain region and the second gate region of the first cell are located between the first and second bit-line rings. The first drain region and the first gate region of the second cell is located within the second bit-line ring. The second drain region of the first cell and the first drain region of the second cell are located between the two immediately-adjacent word-lines.

Described herein are systems, methods, and other techniques for identifying redundant parameters and reducing parameters for testing a device. A set of test values and limits for a set of parameters are received. A set of simulated test values for the set of parameters are determined based on one or more probabilistic representations for the set of parameters. The one or more probabilistic representations are constructed based on the set of test values. A set of cumulative probabilities of passing for the set of parameters are calculated based on the set of simulated test values and the limits. A reduced set of parameters are determined from the set of parameters based on the set of cumulative probabilities of passing. The reduced set of parameters are deployed for testing the device.

An integrated circuit for a semiconductor device that includes a first terminal for receiving a power supply voltage, a second terminal to which a load is to be coupled, and first and second metal-oxide-semiconductor (MOS) transistors each having a drain electrode and a source electrode, the source electrodes being respectively coupled to the first and second terminals. The integrated circuit includes a first line coupled to the drain electrode of the first MOS transistor and the drain electrode of the second MOS transistor, a second line to which a first voltage lower than the power supply voltage is applied, a first device configured to couple the first line and the second line, to prevent the first line from being brought into a floating state, and a detection circuit configured to detect a first abnormality in at least the first MOS transistor based on a voltage level of the first line.

A magnetic field transducer mounting apparatus can include a first mount configured to fixedly couple to a side surface of a wafer test fixture magnet, and a second and third mount configured to adjustably position a magnetic field transducer in a predetermined location proximate a face of the wafer test fixture magnet.

The present disclosure provides a wafer probe card including: a non-magnetic printed circuit board (PCB) having a first side and a second side opposite the first side, the first side configured to face a magnet; a plurality of connection structures provided on the first side of the non-magnetic PCB; and a Hall sensor unit fixedly provided on the first side of the non-magnetic PCB, the Hall sensor electrically connected to at least one of the plurality of connection structures.

A circuit calibration system can include a calibration voltage source, a calibration output line, and a variable voltage system connected between the calibration voltage source and the calibration output line. The variable voltage system can be configured to provide a variable calibration voltage to the calibration output line.

An apparatus for detecting an anomaly in an electronic system embodying at least two integrated circuits, and where necessary, removing/mitigating the anomaly. The anomaly detection is based on sensing the characteristics of either the current, the voltage, or both the current and voltage of the supply rail connected to the at least two integrated circuits. When an anomaly occurs, the anomaly is detected by one sensing circuit sensing that the characteristics are different from that when the electronic system is functioning normally.

Embodiments of the present disclosure provide methods, systems, apparatus, and computer program products are for detecting whether a suspect component such as an integrated circuit (IC) or a system-on-chip (SoC) is recycled. Specifically, various embodiments involve processing power supply rejection ratio (PSRR) data obtained from a low drop-out regulator (LDO) used for the suspect component using a recycle detection machine learning model to generate a recycle prediction. In particular embodiments, the recycle detection machine learning model is developed based at least in part on degradation of PSRRs of LDOs. Accordingly, a determination is made as to whether the suspect component is recycled based on the recycle prediction. If so, then an indication that the suspect component is recycled is provided.

A method and non-transitory computer-readable medium for performing multiple tests on a device under test (DUT) are provided. The method includes inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.