An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.

A semiconductor device includes a first input conductive plate on which a plurality of first semiconductor chips arranged in a first direction, a first output conductive plate extending in the first direction and being provided adjacent to the first input conductive plate, a case having first to fourth side walls for accommodating the first input conductive plate and the first output conductive plate, first main current wiring members, each of which connects one of the first output electrodes to a front surface of the first output conductive plate, a first detection terminal disposed in the first side wall, and a first detection wiring member connecting the front surface of the first output conductive plate to the first detection terminal. The first output conductive plate is disposed closer to the first side wall than is the first input conductive plate.

Embodiments of the present application disclose a fixing device and fixing method for chip test and a chip tester. The fixing device for chip test includes: a carrier with a fixing chamber for fixing a chip formed inside, a plurality of adjustors being disposed on sidewalls of the fixing chamber and configured to be extended or retracted to adjust a position of the chip in two orthogonal directions within a horizontal plane; and a top cover configured to cooperate with the carrier to fix the chip in a vertical direction, wherein at least one adjustable pressing cover is disposed at a bottom of the top cover, so as to autonomously adjust a pressing force applied to the chip by the pressing cover in the vertical direction. The present application is suitable for fixing chips with various overall dimensions, and can adaptively adjust a pressing force.

A method for measuring frequency domain characteristics of a PDN having an output terminal connected to a power supply end of a functional circuit. The method includes: a to-be-measured output interface of the functional circuit is acquired; the to-be-measured output interface is controlled to output a first level signal having a first preset rule; remaining at least one output interface of the functional circuit, other than the to-be-measured output interface, is controlled to output a second level signal having a second preset rule according to a first frequency; changing voltage values corresponding to the first frequency and output by the to-be-measured output interface are acquired; and a characteristic impedance of the PDN at the first frequency is determined based on the changing voltage values corresponding to the first frequency.

A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

The present disclosure discloses a Single-Event Transient (SET) pulse measuring circuit capable of eliminating impact thereof, and an integrated circuit chip. The SET pulse measuring circuit capable of eliminating impact thereof includes four parts: a SET pulse test chain, a latch circuit, a flip-flop test circuit, a latching self-trigger circuit. The integrated circuit chip is provided with a test chain module and two sets of SET pulse measuring circuits capable of eliminating impact thereof, and inputs of the two sets of SET pulse measuring circuits capable of eliminating impact thereof are the same and each are connected to an output terminal of the test chain module.

A test logic method (500) for an Integrated Circuit Device (100) including a main Integrated Circuit device (200) and an auxiliary Integrated Circuit device (300) having an auxiliary logical internal state (340). The method (500) includes a request (610), wherein a main configuration register (210) requests (610) testing (740) of an auxiliary logic circuit (330) via an auxiliary test logic circuit (350), testing (740), wherein the auxiliary test logic circuit (350) tests (740) the auxiliary logic circuit (330), displaying (750), wherein the auxiliary logic circuit (330) displays (750) the auxiliary logical internal state (340), and a reading (670), wherein the main configuration register (210) reads (670) the auxiliary logical internal state (340).

An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

A method for detecting the aging of a power electronic device that comprises at least one semiconductor component including a step of providing of an excitation signal, which is designed to trigger a flow of an at least approximately semi-sinusoidal excitation current through the semiconductor component in order to introduce a power loss into the semiconductor component, a step of uploading a temperature signal, which represents the temporal course of the temperature of the semiconductor component, and a step of determining of an aging value that represents the aging of the power electronic device by using the temperature signal.

A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die and coupled to each other through a plurality of through-electrodes and a reference through-electrode, wherein the base die includes a first test circuit suitable for transferring a test oscillating signal to at least one target through-electrode among the through-electrodes, and outputting a test output signal by comparing a test base signal generated based on the test oscillating signal, with a test core signal transferred through the reference through-electrode, during a test operation; and wherein each of the core dies includes a second test circuit suitable for generating the test core signal corresponding to the test oscillating signal transferred through the target through-electrode, and transferring the test core signal to the reference through-electrode, during the test operation.