A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

An ATE testing system (900, 1000) for millimetre wave (mmW) packaged integrated circuits (820) includes: at least one packaged integrated circuit (820); a radio frequency, RF, socket (700) configured to receive the at least one packaged integrated circuit (820) and facilitate routing RF signals thereto via at least one input connector and at least one output connector; and at least one interface configured to couple a tester to at least one packaged integrated circuit (820). The RF socket (700) includes a mmW absorber (1010) located adjacent the at least one output connector of the RF socket (700).

An ID chip socket according to an embodiment disclosed herein includes: a contactor configured to be fixed to an upper side of the frame; a socket-conductive part penetrating the contactor in a vertical direction and configured to enable electrical connection in the vertical direction; an ID chip fixed to an upper side of the socket-conductive part and electrically connected to the socket-conductive part; and a cover configured to cover an upper surface of the ID chip and to be fixed to at least one of the contactor and the frame.

A semiconductor device includes a leakage distribution estimation system. The system includes: a parameter sampling unit suitable for selecting sample values for parameters, which are changed according to a process variation of the semiconductor device; a data transformation unit suitable for transforming the sample values selected by the parameter sampling unit into Gaussian sample values; a leakage data generation unit suitable for generating leakage data of the semiconductor device by performing a leakage simulation using node bias information on switching elements included in the semiconductor device, information extracted for leakage components of the switching elements, and the Gaussian sample values; and a Gaussian mixed model (GMM) modeling unit suitable for clustering the leakage data into a plurality of clusters, generating Gaussian components corresponding to the respective clusters using the leakage data of the clusters and mixing the Gaussian components thereby to determine a leakage distribution of the semiconductor device.

A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.

A method and apparatus for controlling a tester, related medium and electronic device are provided. The apparatus includes a vibration data collector attached on a side wall of the tester to collect vibration data from the tester during operation thereof. The method includes: receiving the vibration data collected by the vibration data collector; comparing the vibration data with a predetermined threshold to generate a comparison result; and controlling an operating state of the tester based on the comparison result. This method may timely identify any instability of the tester and prompt for repair if necessary. It substantially reduces the time and material costs associated with a test, and thus reduces the non-chip-attributable defect rate.

A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage. Further, the method includes raising the test stage toward the test probe until an alignment feature of the test probe engages a first solder ball of the die, and fine aligning the die with reference to the test probe by continuing to raise the test stage until a second solder ball of the die fits into a test cup of the test probe.

Power control arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes an integrated circuit device comprising one or more processing cores and a power domain configured to distribute a supply voltage to the one or more processing cores. The assembly also includes a charge injection circuit coupled to the power domain of the integrated circuit device, and configured to selectively couple electric charge into the power domain to predictively offset at least portions of voltage transients in the power domain.