Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Embodiments herein describe techniques for binning integrated circuits (ICs) using an adaptive binning system that can re-bin the ICs in response to receiving a new or updated test specification. Unlike static binning systems, in one embodiment, the binning system receives measured test data from a testing system. Put differently, instead of a testing apparatus simply indicating whether an IC does (or does not) satisfy the criteria in the test specification, the testing apparatus provides measured test data to the binning system. The binning apparatus can then store the received test data. As such, if a new test specification is received or generated, the binning system can use the already saved test data to re-bin the ICs using the criteria in the new test specification without having to re-test the ICs. In this manner, the binning system can re-categorize the ICs as customer needs or customer demand changes.

An integrated circuit for measuring a signal, including a parametric pin measurement unit (PPMU) that sends a forced signal, the PPMU having a first amplifier, a second amplifier with an output terminal connected to the input terminals of the first amplifier through a common resistor; a voltage-to-current convertor connected to a PPMU output and having a first output and a second output; n channel MOSFETs connected to the first output of the voltage-to-current converter; p channel MOSFETs connected to the second output of the voltage-to-current converter; a buffered amplifier connected to an output port between the n channel MOSFETs and the p channel MOSFETs; and a resistance divider connected to the output of the buffered amplifier.

There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.

A method for producing, on a metal retainer plate, an electronic module undergoing an electrical test. Prior to a final overmolding that forms the exterior envelope of the electronic module, there is performed a limited initial overmolding of at least one electrical-connection zone, thus surrounding a free-end portion of a rough form of an insulating second securing bar, by establishing between these a non-conducting overmolded bridge, a first securing bar is cut off from a component or element in order to electrically isolate said at least one electrical-connection zone, and an electrical test is performed on the zone prior to the final overmolding of the exterior envelope, with the electronic component or element being secured to the insulating second securing bar and to the retainer plate by the overmolded bridge.

A compound may include a set of integrated circuits. An integrated circuit, of the set of integrated circuits, may include calibration standards integrated at a silicon layer of the integrated circuit. The integrated circuit may be included in a package, and a calibration standard, of the calibration standards, may be available to at least one port of a set of ports of the integrated circuit.

[Objective] To provide a wiring substrate for electronic component inspection apparatus which includes a first laminate of resin layers with a plurality of pads for probe provided on its front surface and a second laminate of ceramic layers disposed on the back side of the first laminate and which, despite joining by brazing of a plurality of studs to the back surface of the second laminate, is free from deformation of resin of the first laminate caused by softening or the like and from accidental formation of a short circuit between brazing material layers used for the brazing and external connection terminals formed on the back surface of the second laminate. [Means for Solution] A wiring substrate for electronic component inspection apparatus 1 which includes a first laminate 3 composed of a plurality of stacked resin layers j1 to j3 and having a plurality of pads for probe 9 on its front surface 5, a second laminate 4 disposed on a back surface 6 side of the first laminate 3 and composed of a plurality of stacked ceramic layers c1 to c3, and a plurality of studs 20a joined to a back surface 8 of the second laminate 4 and in which the resin layers j1 to j3 of the first laminate 3 are formed of a resin having a thermal deformation temperature of 300 C. or higher, and the studs 20a are joined to surfaces of metal layers 16 formed on the back surface 8 of the second laminate 4 via brazing material layers 28, respectively.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.