Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.

A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The first probe pillar has a first protruding portion protruding from the bottom surface. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The redistribution structure is in direct contact with the flexible substrate and the first probe pillar. The redistribution structure includes a dielectric structure and a wiring structure in the dielectric structure. The wiring structure is electrically connected to the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.

A power monitor includes a detecting circuit, a processing circuit, and a warning circuit. The detecting circuit detects a first abnormal condition of a primary side circuit and a second abnormal condition of a secondary side circuit. The processing circuit calculates a first class and a first occurring number of the first abnormal condition, and calculates a second class and a second occurring number of the second abnormal condition. The processing circuit determines whether the first occurring number is larger than a first predetermined number corresponding to the first class; if it is, the processing circuit outputs a first abnormal signal. The processing circuit determines whether the second occurring number is larger than a second predetermined number corresponding to the second class; if it is, the processing circuit outputs a second abnormal signal. The warning circuit outputs a warning signal according to the first or the second abnormal signal.

Described herein are systems, methods, and other techniques for identifying redundant parameters and reducing parameters for testing a device. A set of test values and limits for a set of parameters are received. A set of simulated test values for the set of parameters are determined based on one or more probabilistic representations for the set of parameters. The one or more probabilistic representations are constructed based on the set of test values. A set of cumulative probabilities of passing for the set of parameters are calculated based on the set of simulated test values and the limits. A reduced set of parameters are determined from the set of parameters based on the set of cumulative probabilities of passing. The reduced set of parameters are deployed for testing the device.

According to one aspect, an integrated circuit includes: an electronic module configured to generate a voltage at an output, and an electronic control circuit coupled to an output of the electronic module, the electronic control circuit comprising an emissive electronic component. The electronic control circuit is configured to cause the emissive electronic component to emit light radiation as a function of a value of the voltage at the output of the electronic module relative to a value of an operating voltage of the electronic module, and the operating voltage is specific thereto during normal operation of this electronic module. The light radiation emitted by the emissive electronic component is configured to diffuse to an outer face of the integrated circuit.

A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.

Provided is a wire bonding state determination device which determines a bonding state between a pad and a wire after the wire is bonded to the pad. The wire bonding state determination device includes: a waveform detector which makes an incident wave incident to the wire, and detects a transmission waveform of the wire and a reflection waveform from a first bonding surface between the pad and the wire; and a bonding determination unit which determines the bonding state between the pad and the wire based on the transmission waveform and the reflection waveform detected by the waveform detector.