The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

A flexible probe card according to the present invention includes a compression layer; a transport layer coupled to the compression layer; and a contact layer coupled to the transport layer. The compression layer is formed of encapsulated closed cell polyurethane foam. The transport layer includes connectors for coupling the flexible probe card to a tester. The contact interface layer includes embedded conductive wires placed in a fixed grid pattern in a silicon rubber layer without a specific connector pattern associated either with the transport layer or a device under test.

The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

A method for increasing a reliability of a transducer is provided. The transducer has a first and a second IC, wherein the two ICs each have substantially the same monolithically integrated circuit components with one sensor apiece, and a signal contact for bidirectional data transmission. A reference contact on each of the two ICs is connected to or disconnected from the signal contact by a controllable switch, and a signal generated as a function of the physical quantity sensed by the relevant sensor is applied to the signal contact. The two ICs are integrated into a common IC package, and a supply voltage contact of the first IC is connected to a first package contact, and the first package contact is connected to a first terminal of a control unit, and the supply voltage contact of the second IC is connected to a second package contact.

A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

A method for detecting the aging of a power electronic device that comprises at least one semiconductor component including a step of providing of an excitation signal, which is designed to trigger a flow of an at least approximately semi-sinusoidal excitation current through the semiconductor component in order to introduce a power loss into the semiconductor component, a step of uploading a temperature signal, which represents the temporal course of the temperature of the semiconductor component, and a step of determining of an aging value that represents the aging of the power electronic device by using the temperature signal.

A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

A method detects electromigration in a field replaceable unit. An integrated circuit, which is within a field replaceable unit (FRU) in an electronic device, is quiescented. An isolation power switch applies a test voltage from a field power source to a target voltage rail in the integrated circuit. An isolation power switch isolates the target voltage rail from the field power source. A voltage sensor coupled to the target voltage rail measures a field voltage decay rate for the target voltage rail. A voltage record comparator logic within the integrated circuit compares the field voltage decay rate to an initial voltage decay rate for the target voltage rail. In response to a difference between the field voltage decay rate and the initial voltage decay rate for the target voltage rail exceeding a predetermined limit, a signal is sent to an output device.