An attenuation apparatus and a test system. The attenuation apparatus includes a signal transmission channel and at least one radiation loss structure, wherein the signal transmission channel is configured to perform transmission attenuation on the energy of a transmitted signal; the radiation loss structure is arranged in the signal transmission channel; the radiation loss structure has a first operating state and a second operating state; when the radiation loss structure is in the first operating state, the radiation loss structure is configured to perform radiation attenuation on the energy of a signal transmitted by the signal transmission channel; and when the radiation loss structure is in the second operating state, the radiation loss structure is configured to perform transmission attenuation on the energy of the signal transmitted by the signal transmission channel.

A ground-loss detection circuit for an integrated circuit, (IC) device including a first dynamic threshold metal oxide semiconductor (DTMOS) device operably coupled between a first ground plane of the IC device and at least one further ground plane of the IC device, at least one of the first and at least one further ground planes comprising an external ground connection of the IC device, at least one further DTMOS device operably coupled between the first and at least one further ground planes of the IC device in an opposing manner to the first DTMOS device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further DTMOS devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further DTMOS device(s).

A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

Integrated circuit systems, such as sensor systems, having on-board-diagnostic (OBD) circuits for the detection of errors presenting internal to the systems are disclosed, along with related methods. In one embodiment, an ADC multiplexer receives analog output readback from an output driver and provides a signal triggering an OBD circuit for internal error indication performed completely independent of digital-to-analog converters (DAC) and output drivers, which can be the point of failure.

Measurement data are produced by measuring characteristics of a semiconductor device. Target parameters are selected among a plurality of parameters of a device model where the device model is configured to perform a simulation based on device data and output simulation result data indicating the characteristics of the semiconductor device. Initial value sets corresponding to different combinations of initial values of the target parameters are selected. Local minimum values are determined based on reinforcement learning. Each local minimum value corresponds to a minimum value of a difference between the measurement data and the simulation result data with respect to each initial value set. Optimal values of the target parameters are determined based on the plurality of local minimum values. The device model capable of precisely predicting characteristics of the semiconductor device is generated by determining the parameters of the device model using the optimization scheme based on the reinforcement learning.

Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.

A method and non-transitory computer-readable medium for performing multiple tests on a device under test (DUT) are provided. The method includes inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.