Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.

A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and/or determine a temperature map or a current map of the target integrated circuit.

The present disclosure is directed to methods and systems for analyzing integrated circuits. The method includes performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model. The method also includes scanning a netlist of a power distribution network, the power distribution network electrically connected to the power-receiving circuit. The method further includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method further includes performing a second RC extraction process on the selection of circuit elements and producing a second RC model. The method further includes performing a simulation process on the power-receiving circuit and the power distribution network using the first and second RC models.

A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT.

A reading circuit for a die ID in a chip is provided. The reading circuit includes a chip damage detection circuit, a switch selector, a fuse controller, and a fuse device, where the fuse device stores the die ID; the fuse controller reads the die ID from the fuse device; the chip damage detection circuit detects whether a processor in the chip is capable of operating properly, so as to obtain a detection result, and notify the switch selector of the detection result; and when the detection result is that the processor is capable of operating properly, the switch selector connects the processor and the fuse controller; and when the detection result is that the processor is not capable of operating properly, the switch selector connects the fuse controller and a maintenance device that is located outside the chip.

In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

A device and a method for monitoring and analysis utilize unintended electromagnetic emissions of electrically powered components, devices or systems. The emissions are received at the antenna and a receiver. A processor processes and measures change or changes in a signature of the unintended electromagnetic emissions. The measurement are analyzed to both record a baseline score for future measurements and to be used in determining status and/or health of the analyzed system or component.

An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.