According to a certain embodiment, the semiconductor device includes: an integrated circuit unit; a command control unit configured to execute command control for the integrated circuit unit on the basis of a command, an address, and/or data, each supplied from an outside; an internal state control unit configured to detect an operating state inside the integrated circuit unit, and to provide an internal state signal indicating a first state or a second state in accordance with the detected operating state; and an instruction rejection control unit configured to instruct the internal state control unit to compulsorily turn the internal state signal to the first state if an operation of the integrated circuit unit has not been completed even after a predetermined maximum monitoring time has elapsed, and to instructs the command control unit to reject an input/output operation of the command, the address, and/or the data.

An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

A detection circuit and an integrated circuit. The detection circuit is used for detecting the drift or an open circuit of a first capacitor (C1) on a filtered second power source terminal (220), and the second power source terminal (220) is suitable for acquiring a power source voltage from an unfiltered first power source terminal (210) by means of a first resistor (R1), and is suitable for being coupled to a reference electric potential terminal (230) by means of the first capacitor (C1). The detection circuit comprises a second resistor (R2) and a second capacitor (C2) that are connected in series and coupled between the first power source terminal (210) and the reference electric potential terminal (230), wherein the second resistor (R2) and the second capacitor (C2) have the same time constant as the first resistor (R1) and the first capacitor (C1).

A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

A method of testing a self-contained device under test having at least a circuit under test and a power source is provided. The method may include at least temporarily enabling power from the power source to the circuit under test, determining a first voltage across the circuit under test, determining a second voltage across the circuit under test after a test duration, and calculating an average current of the circuit under test based at least partially on the first voltage, the second voltage and the test duration.

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.

Techniques and examples pertaining to variation calibration for envelope tracking on chip are described. Envelope tracking (ET) statistics among multiple wireless-capable mobile devices (e.g., smartphones) may be collected in laboratory. Optimal ET parameters may be determined based on ET statistics. An ET setting file may be generated for ET factory calibration. In production lines, the ET setting file may be loaded into each mobile device for ET factory calibration.