An apparatus for testing components for use in a power system includes at least one power amplifier circuit configured to be coupled to the component and a control circuit configured to operate the power amplifier circuit responsive to at least one state of a component emulator for the component included in a system emulator for the power system. The component emulator may include at least one power electronics converter circuit and the control circuit may be configured to control at least one of a voltage and a current of the at least one power amplifier circuit responsive to at least one of a voltage and a current of the at least one power electronics converter circuit. The control circuit may be further configured to control the component emulator responsive to at least one state of the at least one power amplifier circuit.

A field-programmable gate array includes a memory, a firmware state machine, a register, and an interconnect structure. The memory is configured to store a plurality of configurations. Each of the plurality of configurations has at least one parameter associated therewith. The firmware state machine is configured to read the parameters stored in the memory. The register is configured to have the parameters associated with the plurality of configurations written thereto. The interconnect structure is configured to transmit the parameters between the firmware state machine and the register. The interconnect structure is configured to receive the parameters associated with the plurality of the configurations simultaneously and the interconnect structure is configured to transmit the received parameters associated with the plurality of configurations to the register simultaneously.

Various implementations described herein relate to systems and methods for determining abnormal leakage current of a capacitor by determining a number of recent leakage current values for the capacitor and determining a maximum upper limit, minimum upper limit, maximum lower limit, and minimum lower limit based on leakage current values different from the recent leakage current values. A present upper limit and a present lower limit are determined for the recent leakage current values. Abnormal leakage current is determined in response to determining that the present upper limit being greater than an upper threshold (determined based on the maximum upper limit and the minimum upper limit) or the present lower limit being less than a lower threshold (determined based on the maximum lower limit and the minimum lower limit).

A measurement apparatus includes external terminals configured for connection to a device-under-test (DUT), the external terminals including first and second force terminals and first and second sense terminals. The measurement apparatus further includes a controller and a feedback loop configured in a current feedback mode to sense a current flowing from the first force terminal to the second force terminal, and in a voltage feedback mode to sense a voltage across the first and second sense terminals. The measurement apparatus further includes a measurement path configured to measure a least one of a voltage and current across a pair of the external terminals and to supply the measured at least one of the voltage and current to the controller.

Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

A direct-current power supply applies a DC voltage to test semiconductor devices. A current detection unit detects a leakage current of a test circuit in which test semiconductor devices are included. A measuring instrument records a pulse waveform of the leakage current. An analyzer analyzes reliability of test semiconductor devices included in the test circuit based on the recorded pulse waveform.

Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

A device binning and/or matching process includes measuring with a testing device currents and/or voltages of a device with respect to time, determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time, and outputting with the testing device the binning and/or matching criteria for the device. A system and power module are also disclosed.

An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.