Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

A method for predicting an operation parameter of an integrated circuit includes the following steps. A plurality of cells used by the integrated circuit are provided. A voltage-frequency sweep test is performed on each of cells through a test model to generate a plurality of parameters, wherein the parameters correspond to a voltage value. A lookup table is established according to the parameters. A timing signoff corresponding to the integrated circuit is obtained. A timing analysis is performed on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and the operation parameter of the integrated circuit is predicted according to the critical timing path.

A method for predicting an operation parameter of an integrated circuit includes the following steps. A plurality of cells used by the integrated circuit are provided. A voltage-frequency sweep test is performed on each of cells through a test model to generate a plurality of parameters, wherein the parameters correspond to a voltage value. A lookup table is established according to the parameters. A timing signoff corresponding to the integrated circuit is obtained. A timing analysis is performed on a plurality of timing paths of the integrated circuit according to the timing signoff and the parameters of the lookup table to obtain a critical timing path, and the operation parameter of the integrated circuit is predicted according to the critical timing path.

An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

Various implementations described herein relate to systems and methods for determining abnormal leakage current of a capacitor by determining a number of recent leakage current values for the capacitor and determining a maximum upper limit, minimum upper limit, maximum lower limit, and minimum lower limit based on leakage current values different from the recent leakage current values. A present upper limit and a present lower limit are determined for the recent leakage current values. Abnormal leakage current is determined in response to determining that the present upper limit being greater than an upper threshold (determined based on the maximum upper limit and the minimum upper limit) or the present lower limit being less than a lower threshold (determined based on the maximum lower limit and the minimum lower limit).

Systems and methods are disclosed for testing a device under test (DUT) by receiving a test pattern for a functional test, wherein the test pattern includes a test vector, an expected test result, and an expected power consumption; instructing the test system to run a repetitive loop using a selected functional test as the stimulus; at selected steps in the functional test, measuring power consumption of the DUT; and validating the DUT based on validating the test vector and the power consumption with one or more expected test result patterns and expected power consumption patterns.

A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

An automated testing system for power supply units includes a frame, automated test equipment supported by the frame, a test jig supported by the frame and coupled with the automated test equipment, and a robotic arm coupled to the frame. The robotic arm is configured to move a power supply unit onto the test jig to interface with the automated test equipment. The automated test equipment is configured to perform one or more tests on the power supply unit when the power supply unit is interfaced with the automated test equipment, and the robotic arm is configured to move the power supply unit off of the test jig after the one or more tests are completed. Methods of performing automated testing for power supply units are also disclosed.

A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.