A method for detecting a break in connection of a neutral of a three-phase electricity network, implemented in a processing unit of an item of electrical equipment connected to the electricity network includes acquiring, at a time T, a first phase voltage (V1), a second phase voltage (V2) and a third phase voltage (V3) measured by voltage sensors of the item of electrical equipment; evaluating a first quantity representative of a ratio between a maximum voltage and a minimum voltage from the first, second and third phase voltages; if the first quantity is greater than a predetermined threshold: evaluating, based on the first, second and third phase voltages, a second quantity; detecting a break in the neutral at the time T when the second quantity satisfies a predetermined reference criterion.

A semiconductor device test system and a semiconductor device test method are provided. The system includes a device under test (DUT) which provides an output voltage to a load connected to an output terminal, automatic test equipment (ATE) which supplies power to the DUT and measures the output voltage of the DUT, and a current mirror which is connected between the ATE and the DUT. The ATE outputs a reference current to the current mirror, and the DUT provides an output current to the current mirror. The output current is obtained by mirroring the reference current from the ATE.

A semiconductor device test system and a semiconductor device test method are provided. The system includes a device under test (DUT) which provides an output voltage to a load connected to an output terminal, automatic test equipment (ATE) which supplies power to the DUT and measures the output voltage of the DUT, and a current mirror which is connected between the ATE and the DUT. The ATE outputs a reference current to the current mirror, and the DUT provides an output current to the current mirror. The output current is obtained by mirroring the reference current from the ATE.

System and method for autonomous trouble shooting of a unit under test (UUT) having a plurality of replaceable components include: a test station that stores an artificial intelligence (AI) program and a knowledge database (KDB) including acceptable test results for each test point represented by an acceptable test vector, a test probe to test the circuit card assembly; and an operator station to send commands to the test station via the communication network to teach the AI program to capture and store the acceptable test result for each test point of the UUT by the test probe, in the KDB, wherein the AI program commands the test probe to test the UUT, stores the test results in a test result vector, compares the test result vector with the stored acceptable test vector, and displays recommendation as which replaceable component in the UUT to be repaired or replaced.

A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.

Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

A test and measurement instrument including a voltage source configured to output a source voltage, a current sensor, and one or more processors. The one or more processors are configured to determine an estimation of a load of an unknown connected device under test based on the source voltage, the current sensor, and a voltage of the connected device under test without any prior knowledge of the connected device under test.

A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.