During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Disclosed are techniques for using a sense amplifier for the voltage path having an adjustable gain and a current amplifier for the current path having an adjustable sample-hold interval for demodulation of in-band ASK data in power transmitting devices of a wireless charging system. The sample-hold interval may be adjusted as a function of the error rate of the demodulated data and used to sample the modulated current when the adjustable gain of the voltage path is not able to track the modulated voltage. The adjustable sample-hold may function as a variable reference of a comparator used to compare the sampled current to generate the sensed current. A controller may flexibly adjust the gain, adjust the sample-hold interval, and/or select the sensed voltage or the sensed current path for further filtering, demodulation, decoding, and processing depending on the error rate under various loading, coupling scenarios, and phases of power transfer.

In an embodiment a method for testing a digital electronic circuit includes coupling an external test equipment to a digital electronic circuit in order to apply an external voltage signal to the digital electronic circuit when an automatic test pattern generation (ATPG) procedure with a given test pattern is performed, wherein a value of the external voltage signal is controlled by the external test equipment and measuring, at the external test equipment, the digital supply voltage at an output of the voltage regulator and at an input of the internal digital circuitry, wherein the external voltage signal is applied to the differential inputs of the op-amp voltage regulator through an adaptation circuit to obtain determined values of the digital supply voltage.

Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

According to one embodiment, a multichannel switch integrated circuit (IC) includes a multichannel switch circuit and a common test terminal. The multichannel switch circuit includes a plurality of switch circuitries. Each of the switch circuitries includes: an output transistor that outputs an output signal through an output terminal; an overcurrent detection circuit that detects a detection current according to a current flowing through the output transistor; and a diode having an anode that receives the detection current. The common test terminal is connected to each channel switch circuitry, connected to the overcurrent detection circuit through the diode, and connected to a cathode of the diode.

A system may include a trim circuit configured to provide a trim signal to a circuit under test. The trim circuit may be configured to adjust a trim value of the trim signal based on a selection signal and a value signal. The trim signal may cause a key characteristic of the circuit under test to change based on the adjusted trim value. The system may include a production tester configured to determine whether the key characteristic is within a threshold range. Responsive to the key characteristic being within the threshold range, the production tester may stop performing the trim procedure on the circuit under test. Responsive to the key characteristic not being within the threshold range, the production tester may adjust the value signal based on whether the key characteristic is greater than or less than the threshold range.

A method for estimating jitter of a clock-signal-under-test includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method includes generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the phase-adjusted clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter estimate using an estimated standard deviation of a distribution of edges of the clock signal based on the N digital time codes for each of the P phase adjustments.

A sensing electronic device includes a substrate, and a reference voltage control unit. The sensing array is arranged on the substrate, and includes a first sensing electrode and a second sensing electrode. The reference voltage control unit is electrically connected to the sensing array. In an operation period, the reference voltage control unit has a first voltage, the first sensing electrode has a second voltage, and the second sensing electrode has a third voltage, wherein a difference between the first voltage and the second voltage is different from a difference between the first voltage and the third voltage.

A test and measurement instrument including a voltage source configured to output a source voltage, a current sensor, and one or more processors. The one or more processors are configured to determine an estimation of a load of an unknown connected device under test based on the source voltage, the current sensor, and a voltage of the connected device under test without any prior knowledge of the connected device under test.