A method for diagnosing analog circuit fault based on cross wavelet features includes steps of: inputting an excitation signal to an analog circuit under test, and collecting time domain response output signals to form an original data sample set; dividing the original data sample set into a training sample set and a test sample set; performing cross wavelet decomposition on both sets; applying bidirectional two-dimensional linear discriminant analysis to process the wavelet cross spectra of the training sample set and the test sample set, and extracting fault feature vectors of the training sample set and the test sample set; submitting the fault feature vectors of the training sample set to a support vector machine for training an SVM classifier, constructing a support vector machine fault diagnosis model; and inputting the fault feature vectors of the test sample set into the model to perform fault classification.

An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

An analog-circuit fault diagnosis method based on continuous wavelet analysis and an ELM network comprises: data acquisition: performing data sampling on output responses of an analog circuit respectively through Multisim simulation to obtain an output response data set; feature extraction: performing continuous wavelet analysis by taking the output response data set of the circuit as training and testing data sets respectively to obtain a wavelet time-frequency coefficient matrix, dividing the coefficient matrix into eight sub-matrixes of the same size, and performing singular value decomposition on the sub-matrixes to calculate a Tsallis entropy for each sub-matrix to form feature vectors of corresponding faults; and fault classification: submitting the feature vector of each sample to the ELM network to implement accurate and quick fault classification. The method of the invention has a better effect on extracting the circuit fault features and can be used to implement circuit fault classification accurately and efficiently.

An analog-circuit fault diagnosis method based on continuous wavelet analysis and an ELM network comprises: data acquisition: performing data sampling on output responses of an analog circuit respectively through Multisim simulation to obtain an output response data set; feature extraction: performing continuous wavelet analysis by taking the output response data set of the circuit as training and testing data sets respectively to obtain a wavelet time-frequency coefficient matrix, dividing the coefficient matrix into eight sub-matrixes of the same size, and performing singular value decomposition on the sub-matrixes to calculate a Tsallis entropy for each sub-matrix to form feature vectors of corresponding faults; and fault classification: submitting the feature vector of each sample to the ELM network to implement accurate and quick fault classification. The method of the invention has a better effect on extracting the circuit fault features and can be used to implement circuit fault classification accurately and efficiently.

The disclosure provides high voltage interlock circuit and detection method. The circuit comprises: a power module, a positive electrode of the power module being connected to one end of a current generating module; the current generating module, the other end of the current generating module being connected to a first terminal of a high voltage component module to inject a constant DC current into the high voltage component module; a first voltage dividing module, one end of the first voltage dividing module being connected to a second terminal of the high voltage component module, and the other end of the first voltage dividing module being connected to a negative electrode of the power module and a power ground; and a processing module to determine a fault of the high voltage component module based on a first voltage collected from the second terminal of the high voltage component module.

The disclosure provides high voltage interlock circuit and detection method. The circuit comprises: a power module, a positive electrode of the power module being connected to one end of a current generating module; the current generating module, the other end of the current generating module being connected to a first terminal of a high voltage component module to inject a constant DC current into the high voltage component module; a first voltage dividing module, one end of the first voltage dividing module being connected to a second terminal of the high voltage component module, and the other end of the first voltage dividing module being connected to a negative electrode of the power module and a power ground; and a processing module to determine a fault of the high voltage component module based on a first voltage collected from the second terminal of the high voltage component module.

An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors V.sub.ij to each of fault modes F.sub.i of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors V.sub.ij.sup.F of the voltage signal sample vectors V.sub.ij by using subspace projection; (3) standardizing the extracted fault characteristic vectors V.sub.ij.sup.F to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors V.sub.ij to each of fault modes F.sub.i of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors V.sub.ij.sup.F of the voltage signal sample vectors V.sub.ij by using subspace projection; (3) standardizing the extracted fault characteristic vectors V.sub.ij.sup.F to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.