G01R31/316

Integrity tests for mixed analog digital systems
11959963 · 2024-04-16 · ·

Device for checking the integrity of a digital transmission for an analog output of a system. The analog output may be checked for transient errors that can be attributed to a digital transmission path embedded somewhere within the vehicle system. A test signal is introduced into a digital transmission that can be reassembled from an analog path of the analog output, and, if not, allows the test device to pinpoint that errors are appearing due to the digital path, and not because of the analog output. In this way, debugging an installation of a system becomes easier; obtaining confidence in reliability of a mixed analog and digital system becomes less of a challenge and less time consuming.

SINGLE PIN TEST INTERFACE FOR PIN LIMITED SYSTEMS
20190178937 · 2019-06-13 ·

An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

SINGLE PIN TEST INTERFACE FOR PIN LIMITED SYSTEMS
20190178937 · 2019-06-13 ·

An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

SYSTEMS AND METHODS FOR GENERATING AND MEASURING ELECTRICAL SIGNALS
20250231223 · 2025-07-17 ·

Disclosed is a system for generating and measuring electrical signals. The system comprises a digital-to-analog converter module configured to generate one or more analog signals based on a control signal, and one or more channels. Each channel comprises an output terminal configured to be electrically connected to an electrical device, and a buffer circuit. The buffer circuit is configured to receive an analog signal of the one or more analog signals and to provide to the output terminal a voltage based on the voltage of the received analog signal. The buffer circuit is further configured to be electrically connected to a current source and to allow current to flow between the current source and the output terminal. The system further comprises a voltage measurement system and a current measurement system. The voltage measurement system is configured to measure, for each channel, a voltage indicative of the voltage at the output terminal of the channel. The current measurement system is configured to measure, for each channel, the current flowing through the output terminal of the channel. Also disclosed is method for generating and measuring electrical signals.

SENSOR CIRCUITS, ELECTRONIC DEVICES, AND METHODS FOR PERFORMING INTERNAL CALIBRATION OPERATIONS
20240210509 · 2024-06-27 · ·

A sensor circuit includes a sensing voltage generating circuit configured to generate a sensing voltage set to have a voltage level corresponding to a sensing condition. The sensor circuit also includes a comparison signal generating circuit configured to compare the sensing voltage with at least one reference voltage to generate at least one comparison signal. The sensor circuit further includes a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the reference voltage, based on the at least one comparison signal.

SENSOR CIRCUITS, ELECTRONIC DEVICES, AND METHODS FOR PERFORMING INTERNAL CALIBRATION OPERATIONS
20240210509 · 2024-06-27 · ·

A sensor circuit includes a sensing voltage generating circuit configured to generate a sensing voltage set to have a voltage level corresponding to a sensing condition. The sensor circuit also includes a comparison signal generating circuit configured to compare the sensing voltage with at least one reference voltage to generate at least one comparison signal. The sensor circuit further includes a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the reference voltage, based on the at least one comparison signal.

Failure determination circuit, physical quantity measurement device, electronic apparatus, vehicle, and failure determination method
10256832 · 2019-04-09 · ·

A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

Failure determination circuit, physical quantity measurement device, electronic apparatus, vehicle, and failure determination method
10256832 · 2019-04-09 · ·

A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

MEASURING SYSTEM AS WELL AS METHOD FOR ANALYZING AN ANALOG SIGNAL
20180335474 · 2018-11-22 · ·

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.

MEASURING SYSTEM AS WELL AS METHOD FOR ANALYZING AN ANALOG SIGNAL
20180335474 · 2018-11-22 · ·

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.