An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) detennining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters. The method can convert a single signal into a plurality of signals without losing original measurement information, and extract an independent fault mode feature factor reflecting variations of a circuit structure in different fault modes, can be used to study an associated mode determination rule and successfully complete classification of circuit fault modes.

An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) detennining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters. The method can convert a single signal into a plurality of signals without losing original measurement information, and extract an independent fault mode feature factor reflecting variations of a circuit structure in different fault modes, can be used to study an associated mode determination rule and successfully complete classification of circuit fault modes.

An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors V.sub.ij to each of fault modes F.sub.i of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors V.sub.ij.sup.F of the voltage signal sample vectors V.sub.ij by using subspace projection; (3) standardizing the extracted fault characteristic vectors V.sub.ij.sup.F to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors V.sub.ij to each of fault modes F.sub.i of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors V.sub.ij.sup.F of the voltage signal sample vectors V.sub.ij by using subspace projection; (3) standardizing the extracted fault characteristic vectors V.sub.ij.sup.F to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

An integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and phases with a final phase. The sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. The sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. The integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. The test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

An integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and phases with a final phase. The sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. The sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. The integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. The test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

The present invention relates to a time delay estimation device. The time delay estimation device of the present invention includes a sound signal detection unit configured to detect sound signals through a plurality of microphones, a frequency domain conversion unit configured to convert the detected sound signals into signals of a frequency domain, and a time delay estimation unit configured to estimate a time delay on the basis of a slope of a phase difference between the sound signals converted into the frequency domain.

The present invention relates to a time delay estimation device. The time delay estimation device of the present invention includes a sound signal detection unit configured to detect sound signals through a plurality of microphones, a frequency domain conversion unit configured to convert the detected sound signals into signals of a frequency domain, and a time delay estimation unit configured to estimate a time delay on the basis of a slope of a phase difference between the sound signals converted into the frequency domain.

The present invention relates to a time delay estimation device. The time delay estimation device of the present invention includes a sound signal detection unit configured to detect sound signals through a plurality of microphones, a frequency domain conversion unit configured to convert the detected sound signals into signals of a frequency domain, and a time delay estimation unit configured to estimate a time delay on the basis of a slope of a phase difference between the sound signals converted into the frequency domain.

A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination.