In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

An audio system receives an input signal and, if the input signal has a sparse representation in the frequency domain, comprising components at at least one frequency of interest, the input signal is filtered in at least one band pass filter, such that only components at the or each frequency of interest are passed to an output. The operation is able in some case to analyze the input signal to determine whether the input signal has a sparse representation in the frequency domain.

An audio system receives an input signal and, if the input signal has a sparse representation in the frequency domain, comprising components at at least one frequency of interest, the input signal is filtered in at least one band pass filter, such that only components at the or each frequency of interest are passed to an output. The operation is able in some case to analyze the input signal to determine whether the input signal has a sparse representation in the frequency domain.

An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

An integrated circuit that performs testing of a circuit sub-block is described. This integrated circuit may include the circuit sub-block that performs a function, where the circuit sub-block is implemented in an analog domain using analog components and in a digital domain using digital components. Moreover, the integrated circuit may perform the testing of the circuit sub-block using independent testing of individual components in the circuit sub-block instead of testing the function of the circuit sub-block as a whole. Note that the individual components include the analog components and the digital components. In some embodiments, the testing may include functional safety testing.

An integrated circuit that performs testing of a circuit sub-block is described. This integrated circuit may include the circuit sub-block that performs a function, where the circuit sub-block is implemented in an analog domain using analog components and in a digital domain using digital components. Moreover, the integrated circuit may perform the testing of the circuit sub-block using independent testing of individual components in the circuit sub-block instead of testing the function of the circuit sub-block as a whole. Note that the individual components include the analog components and the digital components. In some embodiments, the testing may include functional safety testing.

A semiconductor device includes a trimming circuit for a power management circuit. The trimming circuit includes an analog to digital converter (ADC) circuit with a comparator circuit, a successive approximation register (SAR) circuit having an input coupled to an output of the comparator circuit, a control circuit coupled to the SAR circuit, a digital to analog converter (DAC) circuit having inputs selectively couplable to digital output signals of the SAR circuit and an output coupled to a first input of the comparator circuit, and a variable resistance circuit configured to be selectively coupled to output signals of the ADC circuit.

An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

A multifunctional substrate inspection apparatus capable of selectively bringing probes into contact. The apparatus has first and second probe bases, to which probes 111-217 having different lengths and capable of contacting surfaces of a substrate, driving means increasing and decreasing an interval between the first and second probe base, an intermediate plate capable of carrying the substrate between the first and second probe bases, a first extendable pole or equivalent support mechanism attached to the first probe base and capable of pressing the substrate with a biasing force based on a driving force of the driving means transmitted via first biasing means, second biasing means for urging the substrate to be inspected away from the intermediate plate, and third biasing means for urging the intermediate plate away from the second probe base, the probes 111-217 being selectively brought into contact with the substrate according to their different lengths.

A circuit configured to: generate a reference clock signal; generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the reference clock signal; update a driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; digitize sense signals resulting from the excitation signal at a frequency having a period that is a third integer number of cycles of the reference clock signal; identify a fourth integer number of sense signal samples; optionally utilize an excitation control signal having a period that is a fifth integer number of cycles of the reference clock signal; and minimize harmonics at the target frequency of the excitation signal based on the first integer number, the second integer number, the third integer number, the fourth integer number, and possibly the fifth integer number.