A circuit configured to: generate a reference clock signal; generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the reference clock signal; update a driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; digitize sense signals resulting from the excitation signal at a frequency having a period that is a third integer number of cycles of the reference clock signal; identify a fourth integer number of sense signal samples; optionally utilize an excitation control signal having a period that is a fifth integer number of cycles of the reference clock signal; and minimize harmonics at the target frequency of the excitation signal based on the first integer number, the second integer number, the third integer number, the fourth integer number, and possibly the fifth integer number.

An oscilloscope comprises a number of analog signal inputs for receiving respective analog input signals, an analog-to-digital converter, ADC, for every analog signal input, each ADC comprising an analog input and a digital output, the analog inputs being coupled to the respective one of the analog signal inputs for receiving the respective analog input signal, and the digital outputs outputting respective digital signals, and a signal processor coupled to the digital outputs of the ADCs that performs predetermined signal processing functions based on at least one of the digital signals and outputs a number of respective digital output signals.

An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.

Embodiments disclosed herein are directed towards systems and methods for electric current leakage detection in a land seismic system. Embodiments may include generating at least one test signal using a digital to analog converter DAC circuitry, wherein the DAC circuitry includes an output operatively connected to earth ground. Embodiments may further include alternately grounding a positive path to an analog to digital converter ADC circuitry during a first time window and a negative path to the analog to digital converter during a second time window while measuring an ADC signal. Embodiments may also include determining an average amplitude of the first time window and the second time window and determining a leakage resistance based upon, at least in part, the average amplitude of the first time window and the second time window.

Embodiments disclosed herein are directed towards systems and methods for electric current leakage detection in a land seismic system. Embodiments may include generating at least one test signal using a digital to analog converter DAC circuitry, wherein the DAC circuitry includes an output operatively connected to earth ground. Embodiments may further include alternately grounding a positive path to an analog to digital converter ADC circuitry during a first time window and a negative path to the analog to digital converter during a second time window while measuring an ADC signal. Embodiments may also include determining an average amplitude of the first time window and the second time window and determining a leakage resistance based upon, at least in part, the average amplitude of the first time window and the second time window.

A method, apparatus and system are provided for the tuning of embedded subsystems of a device under test (DUT) that have analog characteristics. In response to a tester invoking one or more test procedures via a command channel between the tester and a target embedded subsystem of the DUT, test firmware of the invoked tests is loaded into the target embedded subsystem. The target embedded subsystem executes the tests under control of the tester in accordance with test parameters received from the tester over the command channel and in accordance with test commands received from the tester over a test signaling channel. The target embedded subsystem returns results of the one or more tests to the tester via the command channel. The results can be used to trim analog characteristics of the target embedded subsystem and can be stored in memory. The test firmware can then be deleted to free up memory space.

According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

An audio system receives an input signal and, if the input signal has a sparse representation in the frequency domain, comprising components at at least one frequency of interest, the input signal is filtered in at least one band pass filter, such that only components at the or each frequency of interest are passed to an output. The operation is able in some case to analyse the input signal to determine whether the input signal has a sparse representation in the frequency domain.

An example apparatus includes a buffer configured to. when enabled: obtain an input voltage: and provide the input voltage to a first boundary cell: and a second boundary cell configured to. when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.