An example apparatus includes a buffer configured to. when enabled: obtain an input voltage: and provide the input voltage to a first boundary cell: and a second boundary cell configured to. when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.

A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.

A measuring system has an analog-to-digital converter, an acquisition memory, a processing unit, and a display memory. The processing unit is adapted to decode a digital signal according to a protocol creating a decoded signal and to evaluate the decoded signal at a cursor position. The digital data generated by decoding the decoded signal at the cursor position is stored in the display memory. Further, a method for analyzing an analog signal according to a protocol is shown.

A power management device and microprocessor within a System-in-Package (SiP) are provided with communication signals externally available as outputs from the SiP so that they can be configured by an external device. Methods for the configuration of SiPs and Power Management Integrated Circuits (PMICs) packaged within a SiP are also provided.

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with one or more diodes. The test pins may be configured to be coupled to a tester. The one or more diodes may be positioned on one or more internal analog nodes to detect the presence of one or more analog faults. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with one or more diodes. The test pins may be configured to be coupled to a tester. The one or more diodes may be positioned on one or more internal analog nodes to detect the presence of one or more analog faults. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.

A circuit comprises a driver circuit, a processing circuit, and a control circuit. The driver circuit has a first frequency control input and a driver output. The processing circuit has a sense input, a second frequency control input, and a parameter output. And the control circuit has a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.

A circuit comprises a driver circuit, a processing circuit, and a control circuit. The driver circuit has a first frequency control input and a driver output. The processing circuit has a sense input, a second frequency control input, and a parameter output. And the control circuit has a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.