An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.

A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.

A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

A tool is presented herein capable of performing several electrical measurements and generating several electrical outputs. The tool can be configured to perform measurements and provide outputs most commonly utilized when developing and diagnosing failures of a hardware platform based around a microcontroller. The tool can have a form factor and a header configuration compatible for mating with an external microcontroller or minicomputer developer board such as Arduino, UDOO, Raspberry Pi, TI LaunchPad, STM Nucleo, BeagleBone, etc.

A sensor system (1, 1S) including a current DA converter (42) outputting a control current (Ip) of a sensor element (3S), a control unit (4C) generating a control current instruction value (Ipcmd) corresponding to magnitude of the control current and inputting this instruction value to the current DAC, an instruction value sequence generating unit (47) generating, instead of the control current instruction value, an inspection instruction value sequence (RChcmd) in which predetermined inspection current instruction values (Chcmd) inputted to the current DAC are arranged in order and by which failure of the current DAC can be detected, an inspection current detection unit (71) detecting an inspection current value (Ichv) of an inspection current (Ich) outputted from the current DAC, and a failure detection unit (8) detecting failure of the current DAC from an inspection current value sequence (RIchv) in which the inspection current values are arranged in order of detection.

An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.