A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.

Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.

Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.

In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

A real-time clock module includes an oscillation circuit, a storage unit that stores adjustment data used to adjust an oscillation frequency of the oscillation circuit, a data abnormality determination circuit that compares first data based on the adjustment data with second data based on the adjustment data to determine whether or not at least one of the first data and the second data is abnormal, and a flag register that holds a data abnormality flag in which a first value indicating that the first data and the second data are normal, or a second value indicating that at least one of the first data and the second data is abnormal is set, based on a signal from the data abnormality determination circuit.

Methods and structures are described for detecting clock anomalies. Example methods include measuring a duration of a first phase of the clock signal, monitoring a duration of a second phase of the clock signal, and determining whether the duration of the second phase has exceeded the measured duration of the first phase. If so, a clock stop detection signal is asserted. Example structures include a detector circuit having an input for sensing the clock signal. The circuit is operable to measure a duration of a first clock phase instance, to monitor a duration of a second clock phase instance, and to assert an output if the duration of the second clock phase instance exceeds the measured duration of the first clock phase instance.

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

The present application discloses a testing system for integrated circuit device, and signal source and power supplying apparatus. The signal source provides a plurality of supply voltages and a programmable voltage to a plurality of semiconductor chip groups. The signal source includes a power supplying apparatus and a switch set. The power supplying apparatus is configured to generate an additional voltage, a plurality of base voltages, and the programmable voltage. The switch set is disposed between the power supplying apparatus and the plurality of semiconductor chip groups and converts the additional voltage and the plurality of base voltages into the plurality of supply voltages.

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.