The present invention discloses a hysteresis signal detection circuit, comprising: a first MOS transistor, a second MOS transistor, an inverter INV1, an inverter INV2 and an inverter INV3. A gate of the first MOS transistor is connected with an input end, and a drain of the first MOS transistor is connected with an output end through the inverter INV1, the inverter INV2 and the inverter INV3 successively; a source of the first MOS transistor is connected with a drain of the second MOS transistor, and a gate of the second MOS transistor is connected between the inverter INV1 and the inverter INV2; and a resistor R1 is connected between a source and the drain of the second MOS transistor. In the present invention, not only the hysteresis voltage can be adjusted through current and resistance values, which is flexible, but also the hysteresis voltage may not change with power voltage.

Controlling of drop test equipment. A predefined test script is obtained over a machine-machine interface. The test script comprises plurality of test settings for drop testing of a device-under-test, DUT. The drop test equipment is controlled to perform drop testing of the DUT according to the test settings of the test script. Test results are collected and provided to a test report.

A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

A test and measurement system includes a machine learning system configured to communicate with a test automation system, a user interface configured to allow a user to provide one or more user inputs and to provide results to the user, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive one or more user inputs through the user interface, the one or more user inputs at least identifying a selected machine learning system configuration to be used to configure the machine learning system, receive a waveform created by operation of a device under test, apply the configured machine learning system to analyze the waveform, and provide an output of predicted metadata about the waveform.

Described herein are systems and devices for testing electrical circuits. An example integrated test system includes a unit under test (UUT), a test development system operably coupled to the UUT, the test development system being configured to perform in-circuit testing (ICT) on the UUT and a functional platform brain operably coupled to the test development system and the UUT, the functional platform brain being configured to perform functional testing (FCT) on the UUT using a test sequence protocol, wherein the test sequence protocol is configured to facilitate communication between the test development system and the functional platform brain.

An input selector for electrically connecting one of a plurality of test signals from a device under test to a test and measurement instrument includes a multiplexer having multiple inputs, each of the multiple inputs coupled to a different one of the plurality of test signals from the device under test, and having an output of a selected one of the multiple inputs, and an amplifier coupled to the output of the multiplexer for amplifying the selected test signal of the device under test before being sent as an output of the input selector to the test and measurement instrument. In alternative architectures, two or more amplifiers are coupled to the plurality of test signals, and the multiplexer selects an output of one of the two amplifiers to pass to a measurement instrument for testing.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.