An electronic system can be used to monitor temperature. The electronic system can include a characterized dielectric located adjacent to a plurality of heat-producing electronic devices. The electronic system can also include a leakage measurement circuit that is electrically connected to the characterized dielectric. The leakage measurement circuit can be configured to measure current leakage through the characterized dielectric. The leakage measurement circuit can also be configured to convert a leakage current measurement into a corresponding output voltage. A response device, electrically connected to the leakage measurement circuit can be configured to, in response to the output voltage exceeding a voltage threshold corresponding to a known temperature, initiate a response action.

An electronic system can be used to monitor temperature. The electronic system can include a characterized dielectric located adjacent to a plurality of heat-producing electronic devices. The electronic system can also include a leakage measurement circuit that is electrically connected to the characterized dielectric. The leakage measurement circuit can be configured to measure current leakage through the characterized dielectric. The leakage measurement circuit can also be configured to convert a leakage current measurement into a corresponding output voltage. A response device, electrically connected to the leakage measurement circuit can be configured to, in response to the output voltage exceeding a voltage threshold corresponding to a known temperature, initiate a response action.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

A detector is provided that generates a leakage signal corresponding to a current imbalance between a line conductor and a neutral conductor for a load, and selectively injects a test signal into the neutral conductor. A frequency of the test signal substantially corresponds to a utility frequency. The detector measures a first value of the leakage signal, determines if the first value is less than first threshold value, and begins injection of the test signal into the neutral conductor in response to determining that the that first value is less than the first threshold value. In response to injecting the test signal, the detector measures a second value of the signal, determines if the second value is greater than a second threshold value, and disconnects the line conductor from the load in response to determining that the second value is greater than the second threshold value.

A detector is provided that generates a leakage signal corresponding to a current imbalance between a line conductor and a neutral conductor for a load, and selectively injects a test signal into the neutral conductor. A frequency of the test signal substantially corresponds to a utility frequency. The detector measures a first value of the leakage signal, determines if the first value is less than first threshold value, and begins injection of the test signal into the neutral conductor in response to determining that the that first value is less than the first threshold value. In response to injecting the test signal, the detector measures a second value of the signal, determines if the second value is greater than a second threshold value, and disconnects the line conductor from the load in response to determining that the second value is greater than the second threshold value.

An electronic device includes a card interface and a processing module. The card interface is electrically connected to the processing module, and a SIM card or a memory card may be inserted into the card interface. The card interface includes N springs, where N>1; when a memory card is inserted into the card interface, the memory card is electrically connected to the processing module; and when a SIM card is inserted into the card interface, the SIM card is electrically connected to the processing module, and one metal pin of the SIM card is electrically connected to a first spring in the N springs and one spring adjacent to the first spring. The processing module is configured to determine, based on at least a level of the first spring, whether an inserted card is a SIM card or a memory card.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.