The semiconductor structure includes first and second active regions arranged in a first grid oriented in a first direction. The semiconductor structure further includes gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction. The first and second active regions are separated, relative to the second direction, by a gap. Each gate electrode includes a first segment and a gate extension. Each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height H.sub.EXT, where H.sub.EXT≤150 nanometers (nm). Each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular.

A phase shift mask includes a transparent substrate and light-shielding portions. The light-shielding portions include a first light-shielding portion, and over one side of it, a first compensating light-shielding portion, which has a first distance to the first light-shielding portion and a first width smaller than a resolution of an exposing machine utilized for an exposure process using the phase shift mask. The light-shielding portions can further include a second compensating light-shielding portion, having a second distance to another side of the first light-shielding portion and a second width smaller than the resolution of the exposing machine. The first distance and the second distance respectively allow the first and the second compensating light-shielding portion to reduce an exposure at a region corresponding to two sides of the first light-shielding portion during the exposure process. A method manufacturing an electronic component utilizing the phase shift mask is also provided.

A phase shift mask includes a transparent substrate and light-shielding portions. The light-shielding portions include a first light-shielding portion, and over one side of it, a first compensating light-shielding portion, which has a first distance to the first light-shielding portion and a first width smaller than a resolution of an exposing machine utilized for an exposure process using the phase shift mask. The light-shielding portions can further include a second compensating light-shielding portion, having a second distance to another side of the first light-shielding portion and a second width smaller than the resolution of the exposing machine. The first distance and the second distance respectively allow the first and the second compensating light-shielding portion to reduce an exposure at a region corresponding to two sides of the first light-shielding portion during the exposure process. A method manufacturing an electronic component utilizing the phase shift mask is also provided.

An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.

An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.

A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180 phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0 and 180 clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.

A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180 phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0 and 180 clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.

A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.

An alternating phase-shifting mask (Alt-PSM) comprising a 0 phase portion having a first width and a 180 phase portion having a second width greater than the first width. Example differences between the width of the 180 phase portion and the 0 phase portion may be 10 nm, 15 nm, or 20 nm. An Alt-PSM having phase portions of different widths can have an aerial image intensity transmission graph that is symmetric, for example, at 0.2-0.3 intensity.

An alternating phase-shifting mask (Alt-PSM) comprising a 0 phase portion having a first width and a 180 phase portion having a second width greater than the first width. Example differences between the width of the 180 phase portion and the 0 phase portion may be 10 nm, 15 nm, or 20 nm. An Alt-PSM having phase portions of different widths can have an aerial image intensity transmission graph that is symmetric, for example, at 0.2-0.3 intensity.