An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

A multi-channel device and method for measuring the distortion and magnification of objective lens. The multi-channel device for measuring the distortion and magnification of objective lens comprises an illumination system, a reticle stage, a test reticle, a projection objective lens, a wafer stage and a multi-channel image plane sensor, wherein the multi-channel image plane sensor simultaneously measures the image placement shifts between actual image points and nominal image points after a plurality of object plane test marks are imaged by the projection objective lens, and calculates the distortion and magnification errors of the objective lens by fitting, which shortens the measurement time, eliminates the influence of wafer stage errors on the measurement accuracy and improves the measurement accuracy.

A multi-channel device and method for measuring the distortion and magnification of objective lens. The multi-channel device for measuring the distortion and magnification of objective lens comprises an illumination system, a reticle stage, a test reticle, a projection objective lens, a wafer stage and a multi-channel image plane sensor, wherein the multi-channel image plane sensor simultaneously measures the image placement shifts between actual image points and nominal image points after a plurality of object plane test marks are imaged by the projection objective lens, and calculates the distortion and magnification errors of the objective lens by fitting, which shortens the measurement time, eliminates the influence of wafer stage errors on the measurement accuracy and improves the measurement accuracy.

The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.

The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.

Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

A mask includes a first region and a second region. The first region includes a first light-shielding strip and a second light-shielding strip, the second region includes a third light-shielding strip, the first light-shielding strip, the second light-shielding strip is located between the first light-shielding strip and the third light-shielding strip, the first light-shielding strip, the second light-shielding strip and the third light-shielding strip are configured to shield light and bound spaces, and the spaces are configured in such a manner that light is allowed to pass through the spaces. A width of the first light-shielding strip in a first direction is larger than a width of the second light-shielding strip in the first direction, and the width of the second light-shielding strip in the first direction is larger than a width of the third light-shielding strip in the first direction.

A mask includes a first region and a second region. The first region includes a first light-shielding strip and a second light-shielding strip, the second region includes a third light-shielding strip, the first light-shielding strip, the second light-shielding strip is located between the first light-shielding strip and the third light-shielding strip, the first light-shielding strip, the second light-shielding strip and the third light-shielding strip are configured to shield light and bound spaces, and the spaces are configured in such a manner that light is allowed to pass through the spaces. A width of the first light-shielding strip in a first direction is larger than a width of the second light-shielding strip in the first direction, and the width of the second light-shielding strip in the first direction is larger than a width of the third light-shielding strip in the first direction.