Systems and methods for performing local Critical Dimension Uniformity (CDU) modeling in a virtual fabrication environment are discussed. More particularly, local CD variance is replicated in the virtual fabrication environment in order to produce a CDU mask that can be used during a virtual fabrication sequence to produce more accurate results reflecting the CD variance of features that occurs in a pattern for a semiconductor device being physically fabricated.

A computer-implemented method is provided for creating a photolithographic mask. The method includes, in a model building stage, obtaining lithography polygon coordinates from an input lithography target layout. The method further includes, in the model building stage, obtaining mask polygon coordinates from an input mask layout from a test mask. The method also includes, in the model building stage, obtaining correlated mask to lithography features from the lithography polygon coordinates and the mask polygon coordinates. The method additionally includes, in the model building stage, performing linear regression on the correlated mask to lithography features to obtain a machine learning model for predicting an output mask from an input lithography target design. The method further includes, in an inference stage, predicting a given output mask from a given input lithography target design using the machine learning model.

A computer-implemented method is provided for creating a photolithographic mask. The method includes, in a model building stage, obtaining lithography polygon coordinates from an input lithography target layout. The method further includes, in the model building stage, obtaining mask polygon coordinates from an input mask layout from a test mask. The method also includes, in the model building stage, obtaining correlated mask to lithography features from the lithography polygon coordinates and the mask polygon coordinates. The method additionally includes, in the model building stage, performing linear regression on the correlated mask to lithography features to obtain a machine learning model for predicting an output mask from an input lithography target design. The method further includes, in an inference stage, predicting a given output mask from a given input lithography target design using the machine learning model.

A method of manufacturing a semiconductor device structure is provided. The method includes: providing a substrate; forming a photoresist layer on the substrate; patterning the photoresist layer to form a patterned photoresist layer; forming a pitch adjustment layer on the patterned photoresist layer to define a mask pattern; and determining whether the mask pattern meets a specification of semiconductor fabrication processes; when it is determined that the mask does not meet the specification of semiconductor fabrication processes, performing a rework operation to remove the pitch adjustment layer.

A method of manufacturing a semiconductor device structure is provided. The method includes: providing a substrate; forming a photoresist layer on the substrate; patterning the photoresist layer to form a patterned photoresist layer; forming a pitch adjustment layer on the patterned photoresist layer to define a mask pattern; and determining whether the mask pattern meets a specification of semiconductor fabrication processes; when it is determined that the mask does not meet the specification of semiconductor fabrication processes, performing a rework operation to remove the pitch adjustment layer.

A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.

A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.

A simulation apparatus has: a first processing part configured to obtain a value of a parameter in a first set relating to the forming of the pattern; a second processing part configured to obtain a value of a parameter in a second set that is at least partially same as the parameter in the first set and relating to the forming of the pattern; and an integration processing part configured to evaluate, based on the value of the parameter in the first set and the value of the parameter in the second set, a state of the pattern formed on the substrate and a forming condition when the pattern is formed, and to determine based on the result of the evaluation whether or not to make at least one of the first processing part and the second processing part recalculate the value of the parameter in the corresponding set.

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.