An overlay correcting method capable of optimizing correction of an overlay within a scanner correction limit of a scanner of a scanner system, and a photolithography method, a semiconductor device manufacturing method and the scanner system which are based on the overlay correcting method are provided. The overlay correcting method includes collecting overlay data by measuring an overlay of a pattern; calculating correction parameters of the overlay by performing regularized regression using the overlay data, the regularized regression being based on a correction limit of the scanner such that the correction parameters fall within the correction limit of the scanner; and providing the correction parameters to the scanner.

An overlay correcting method capable of optimizing correction of an overlay within a scanner correction limit of a scanner of a scanner system, and a photolithography method, a semiconductor device manufacturing method and the scanner system which are based on the overlay correcting method are provided. The overlay correcting method includes collecting overlay data by measuring an overlay of a pattern; calculating correction parameters of the overlay by performing regularized regression using the overlay data, the regularized regression being based on a correction limit of the scanner such that the correction parameters fall within the correction limit of the scanner; and providing the correction parameters to the scanner.

An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

A method for source mask optimization or mask only optimization used to image a pattern onto a substrate. The method includes determining a non-uniform illumination intensity profile for illumination; and determining one or more adjustments for the pattern based on the non-uniform illumination intensity profile until a determination that features patterned onto a substrate substantially match a target design. The non-uniform illumination intensity profile may be determined based on an illumination optical system and projection optics of a lithographic apparatus. In some embodiments, the lithographic apparatus includes a slit, and the non-uniform illumination profile is a through slit non-uniform illumination intensity profile. Determining the one or more adjustments for the pattern may include performing optical proximity correction, for example.

A method for source mask optimization or mask only optimization used to image a pattern onto a substrate. The method includes determining a non-uniform illumination intensity profile for illumination; and determining one or more adjustments for the pattern based on the non-uniform illumination intensity profile until a determination that features patterned onto a substrate substantially match a target design. The non-uniform illumination intensity profile may be determined based on an illumination optical system and projection optics of a lithographic apparatus. In some embodiments, the lithographic apparatus includes a slit, and the non-uniform illumination profile is a through slit non-uniform illumination intensity profile. Determining the one or more adjustments for the pattern may include performing optical proximity correction, for example.

Computer-implemented systems and methods for eliminating geometrical design rule violations, maintaining mask layout electrical connectivity, reliability verification, and design for manufacturing structural correctness of a mask layout block are provided. Exemplary systems and methods include comparing a feature dimension in a mask layout data file with a design rule in a reference rule file and identifying a design rule violation of a mask layout block if the feature dimension does not match the design rule. Methods may further include automatically correcting the design rule violation by modifying the feature dimension so the feature dimension matches the design rule. A design rule auto-correction tool may be provided and be configured to compare a feature dimension in a mask layout data file with a design rule in a reference rule file and correct the design rule violation. Disclosed embodiments advantageously correct all design rules including dependency rules.

Computer-implemented systems and methods for eliminating geometrical design rule violations, maintaining mask layout electrical connectivity, reliability verification, and design for manufacturing structural correctness of a mask layout block are provided. Exemplary systems and methods include comparing a feature dimension in a mask layout data file with a design rule in a reference rule file and identifying a design rule violation of a mask layout block if the feature dimension does not match the design rule. Methods may further include automatically correcting the design rule violation by modifying the feature dimension so the feature dimension matches the design rule. A design rule auto-correction tool may be provided and be configured to compare a feature dimension in a mask layout data file with a design rule in a reference rule file and correct the design rule violation. Disclosed embodiments advantageously correct all design rules including dependency rules.

A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

Initial source shapes for source mask optimization are determined based on a layout of the lithographic mask. In one approach, a layout of a lithographic mask is received. Different sections of the lithographic mask, referred to as clips, are selected. These clips are applied to a machine learning model which infers source shapes from the clips. The inferred source shapes are used as the initial source shapes for source mask optimization.