A manufacturing method for semiconductor device comprises the steps of: forming a ridge on the surface of an InP substrate; applying a photoresist to the surface of the InP substrate so as to cover the ridge; exposing through a mask an area of the photoresist covering part of an electrode contact layer at the top of the ridge, to form a resist pattern by development; applying a shrink material so as to cover resist pattern defects occurred when forming the resist pattern; forming a crosslinked portion in the defects to repair them by reacting the shrink material with an acid remaining at the exposed interface of the resist pattern; and removing by etching an electrode contact layer exposed from the resist pattern having the repaired defects after stripping away an unreacted shrink material, thereby to obtain a desired processed shape.

A manufacturing method for semiconductor device comprises the steps of: forming a ridge on the surface of an InP substrate; applying a photoresist to the surface of the InP substrate so as to cover the ridge; exposing through a mask an area of the photoresist covering part of an electrode contact layer at the top of the ridge, to form a resist pattern by development; applying a shrink material so as to cover resist pattern defects occurred when forming the resist pattern; forming a crosslinked portion in the defects to repair them by reacting the shrink material with an acid remaining at the exposed interface of the resist pattern; and removing by etching an electrode contact layer exposed from the resist pattern having the repaired defects after stripping away an unreacted shrink material, thereby to obtain a desired processed shape.

A resist composition comprising a base polymer and an acid generator in the form of a sulfonium or iodonium salt of a fluorinated sulfonic acid having a phenylene group which is substituted with a fluorinated cyclic group and a nitro group is provided. The resist composition offers a high sensitivity, reduced LWR and improved CDU independent of whether it is of positive or negative tone.

A resist composition comprising a base polymer and an acid generator in the form of a sulfonium or iodonium salt of a fluorinated sulfonic acid having a phenylene group which is substituted with a fluorinated cyclic group and a nitro group is provided. The resist composition offers a high sensitivity, reduced LWR and improved CDU independent of whether it is of positive or negative tone.

Techniques herein include methods of patterning a substrate using surface energy differences found in some fluorinated polymers or polymers with long chain alkyl functionality that promotes surface or top layer segregation in a bilayer polymer system to facilitate overburden removal when the polymer mixture is deposited over a relief pattern. The method allows for fast removal of the overburden to expose the anti-spacer region which, after acid diffusion and subsequent deprotection, is also soluble in a developer. Incorporating the highly developer-soluble polymer at the top of the top layer removes the need for the remaining polymer to have a specific dissolution rate in developer.

A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

The present invention provides a method of treating a substrate, the method including: performing a first heating process of heat-treating the substrate formed with a film, and a second heating process of heat-treating the substrate after the first heating process is performed; a collection operation of collecting temperature data of a first heating plate which heats the substrate in the first heating process; and a first control operation of adjusting a temperature of a second heating plate which heats the substrate in the second heating process based on the temperature data.

The present invention provides a method of treating a substrate, the method including: performing a first heating process of heat-treating the substrate formed with a film, and a second heating process of heat-treating the substrate after the first heating process is performed; a collection operation of collecting temperature data of a first heating plate which heats the substrate in the first heating process; and a first control operation of adjusting a temperature of a second heating plate which heats the substrate in the second heating process based on the temperature data.

A substrate processing apparatus includes a holder configured to hold, within a processing container, a substrate having a pattern formed of a resist material for EUV lithography on a surface thereof, a rotation driving part configured to rotate the holder, and a light source part including a plurality of light sources configured to emit light to the surface of the substrate held by the holder rotated by the rotation driving part such that a number of rotations of the substrate is 0.5 rpm to 3 rpm.