An exposure apparatus includes: a substrate stage onto which a substrate is to be mounted; an exposure unit radiating an exposure light toward the draw-out electrode on at least one semiconductor chip; a pattern determination unit determining an exposure pattern; and a controller controlling the substrate stage and the exposure unit. The pattern determination unit determines a pattern of a relay wiring connecting the draw-out electrode and a predetermined position with respect to the substrate, by using an output from a measurement unit to measure a position of the semiconductor chips on the substrate to obtain a positional deviation. The controller exposes the relay wiring pattern onto an exposure area extending, on the photosensitive layer, in the uniaxial direction by the exposure unit, while moving the substrate from a first-side in the uniaxial direction to a second-side opposite to the first-side in the uniaxial direction by the substrate stage.

An exposure method includes, in a case of exposing unmeasurable shots which are arranged linearly and whose focus value cannot be measured and a measurable shot which is adjacent to the unmeasurable shots and whose focus value can be measured, exposing alternately the measurable shot and the unmeasurable shots such that the unmeasurable shots are exposed using the focus value of the adjacent measurable shot exposed immediately before the unmeasurable shots.

A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

While a wafer stage moves linearly in a Y-axis direction, surface position information of a wafer surface at a plurality of detection points set at a predetermined interval in an X-axis direction is detected by a multipoint AF system, and by a plurality of alignment systems arranged in a line along the X-axis direction, marks at different positions on the wafer are each detected, and a part of a chipped shot of the wafer is exposed by a periphery edge exposure system. This allows throughput to be improved when compared with the case when detection operation of the marks, detection operation of the surface position information (focus information), and periphery edge exposure operation are performed independently.

A pattern-exposure-apparatus includes illumination-unit that irradiates illumination-light to spatial-light-modulating-element including a plurality of micro-mirrors that are driven to switch between ON-state and OFF-state based on drawing-data, and projection-unit that allows incidence of reflected light from the micro-mirrors of the spatial-light-modulating-element in the ON-state as image-forming-light-flux and that projects image of pattern corresponding to the drawing-data to a substrate. The pattern-exposure-apparatus includes a controller that stores information, which is related to an angular-variation of the image-forming-light-flux generated according to a distribution density of the micro-mirrors of spatial-light-modulating-element which are in the ON-state, together with the drawing-data as recipe-information, and an adjustment-mechanism that adjusts (i) a position or an angle of at least one optical-member in the illumination-unit or the projection-unit or (ii) an angle of the spatial-light-modulating-element, according to the information related to the angular-variation when a pattern is exposed on the substrate by driving the spatial-light-modulating-element based on the recipe-information.

Manufacturing methods are disclosed to produce DOE, HOE and Fresnel optical elements. These methods enable low cost manufacturing with high precision. The methods include lithography, roll-to-roll imprint and UV-casting.

A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

An overlay compensation method and a related system are presented. The method includes: acquiring a first offset vector reflecting the relative position between overlay marks of a middle and a bottom target layers; acquiring a second offset vector reflecting the relative position between the overlay marks of a top and the middle target layers; decomposing the first offset vector into a first compensable component and a first uncompensable component; decomposing the second offset vector into a second compensable component and a second uncompensable component; computing minimum values of the first uncompensable component and the second uncompensable component; computing optimized values for the first compensable component and the second compensable component; and computing a third compensable component of a third offset vector reflecting the relative position between the overlay marks of the top and the bottom target layers.

A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment pattern in a first region, forming, on the substrate, an alignment mark corresponding to the exposed alignment pattern, forming a second photoresist film over the substrate on which the alignment mark is formed, dividing a second pattern into a plurality of regions and exposing the divided regions separately in a second region while performing positioning with respect to the alignment mark, and developing the second photoresist film and forming the second photoresist film having the second pattern, wherein at least a part of the second region is located outside an effective exposure region of an exposure apparatus in exposure of the first pattern.