A smart watch includes a main CPU, a sub CPU, a first display unit, and a second display unit. While the main CPU and the sub CPU cooperate with each other and perform a display operation including a time display, time display processing is performed to at least either of the first display unit or the second display unit according to an operation state.

A smart watch includes a main CPU, a sub CPU, a first display unit, and a second display unit. While the main CPU and the sub CPU cooperate with each other and perform a display operation including a time display, time display processing is performed to at least either of the first display unit or the second display unit according to an operation state.

Provided are an electronic circuit and electronic timepiece that can initialize internal circuits even if chattering occurs when a battery is installed. In the electronic circuit, when the initialization state hold signal is input, the initialization control circuit continues outputting the initialization control signal at the first level until the clock signal is output; and when the initialization state hold signal is input and the clock signal is output, outputs the initialization control signal at the second level cancelling the initialization process to the initialization circuit.

Provided are an electronic circuit and electronic timepiece that can initialize internal circuits even if chattering occurs when a battery is installed. In the electronic circuit, when the initialization state hold signal is input, the initialization control circuit continues outputting the initialization control signal at the first level until the clock signal is output; and when the initialization state hold signal is input and the clock signal is output, outputs the initialization control signal at the second level cancelling the initialization process to the initialization circuit.

Provided is an electronic clock including: a power generator; a secondary battery, which is to be charged with electric power generated by the power generator; a balance information transmitter configured to transmit, to a computer, balance information relating to a transition of a power generation amount or a charging balance of the secondary battery; a connection time period setting module configured to set a connection time period of a connection with the computer based on the balance information; and a communication controller configured to control a start and an end of communication to/from the computer based on the connection time period.

Provided is an electronic clock including: a power generator; a secondary battery, which is to be charged with electric power generated by the power generator; a balance information transmitter configured to transmit, to a computer, balance information relating to a transition of a power generation amount or a charging balance of the secondary battery; a connection time period setting module configured to set a connection time period of a connection with the computer based on the balance information; and a communication controller configured to control a start and an end of communication to/from the computer based on the connection time period.

A power-on control circuit controlling a first output switch and a second output switch is provided. A detecting circuit detects a first voltage to generate a detection signal to a first node. A switching circuit receives the first voltage and a second voltage and transmits the first or second voltage to a second node according to the voltage level of the first node. A setting circuit generates a feedback signal to the first node according to a voltage level of the second node. When the first voltage reaches a first pre-determined value and the second voltage has not reached a second pre-determined value, the switching circuit transmits the second voltage to the second node. When the second voltage reaches the second pre-determined value, the switching circuit transmits the first voltage to the second node.

A power-on control circuit controlling a first output switch and a second output switch is provided. A detecting circuit detects a first voltage to generate a detection signal to a first node. A switching circuit receives the first voltage and a second voltage and transmits the first or second voltage to a second node according to the voltage level of the first node. A setting circuit generates a feedback signal to the first node according to a voltage level of the second node. When the first voltage reaches a first pre-determined value and the second voltage has not reached a second pre-determined value, the switching circuit transmits the second voltage to the second node. When the second voltage reaches the second pre-determined value, the switching circuit transmits the first voltage to the second node.

A control system includes a data monitoring module configured to: obtain one or more status indicators of a voltage regulation system, each status indicator corresponding to an operating parameter of the voltage regulation system; determine a state value of each status indicator at a second time; compare the state value of each status indicator to a state value for that status indicator at a first time, the first time occurring before the second time; determine whether any operating parameter of the voltage regulation system changed state based on the comparison; and if any operating parameter of the voltage regulation system changed state, store a record in a dataset, the record including the state value of all of the status indicators and a time stamp that includes the second time.

To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.