Using a processor and a memory at a worker machine, a gradient vector is computed corresponding to a set of weights associated with a set of nodes of a neural network instance being trained in the worker machine. In an ISA vector corresponding to the gradient vector, an ISA instruction is constructed corresponding to a gradient in a set of gradients in the gradient vector, wherein a data transmission of the ISA instruction is smaller as compared to a data transmission of the gradient. The ISA vector is transmitted from the worker machine to a parameter server, the ISA vector being responsive to one iteration of a training of the neural network instance, the ISA vector being transmitted instead of the gradient vector to reduce an amount of data transmitted from the worker machine to the parameter server for the one iteration of the training.

An optically computed optical coherence tomography (OC-OCT) technology is disclosed. The OC-OCT system performs depth resolved imaging by computing the Fourier transform of the interferometric spectra optically. The OC-OCT system modulates the interferometric spectra with Fourier basis function projected to a spatial light modulator and detects the modulated signal without spectral discrimination. The optical computation strategy enables volumetric OCT imaging without performing mechanical scanning and without the need for Fourier transform in a computer. OC-OCT performs Fourier transform signal processing optically, without the need of mechanical scanning, and before data acquisition unlike traditional OCT methods and systems. The scan-less OCT imaging is achieved through the use of spatial light modulator (SLM) that precisely manipulates light wave to generate output with desired amplitude and phase.

An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values. The first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, with the electrical output port of the PIC connected to one of the electrical input ports of the EIC.

A processor can scan a portion of a vector to identify first nonzero entries. The processor can scan another portion of the vector to identify second nonzero entries. The processor can scale a portion of a matrix using the first nonzero entries to generate first intermediate elements. The processor can scale another portion of the matrix using the second nonzero entries to generate second intermediate elements. The processor can store the first intermediate elements in a first buffer and store the second intermediate elements in a second buffer. The processor can copy a subset of the first intermediate elements from the first buffer to a memory and copy a subset of the second intermediate elements from the second buffer to the memory. The subsets of first and second intermediate elements can be aggregated to generate an output vector.

Disclosed is a method for configuring an MSD parallel adder based on ternary logic operators. Five ternary logic operators that satisfy a sufficient condition for MSD addition are used to configure an MSD parallel adder. During the arrangement of a ternary logic operator, any method in the following may be used: each of ternary operators of n bits is reconfigured into a ternary logic operator each time, and reconfiguration is performed five times for implementation; each of ternary operators of n bits is reconfigured into two ternary logic operators having the same input each time, and reconfiguration is performed three times for implementation; each of ternary operators of n bits is reconfigured into five ternary logic operators of the same time, and reconfiguration is performed once for implementation; corresponding unreconfigurable ternary logic operators are used instead for the foregoing reconfiguration process.

Disclosed is a method for configuring an MSD parallel adder based on ternary logic operators. Five ternary logic operators that satisfy a sufficient condition for MSD addition are used to configure an MSD parallel adder. During the arrangement of a ternary logic operator, any method in the following may be used: each of ternary operators of n bits is reconfigured into a ternary logic operator each time, and reconfiguration is performed five times for implementation; each of ternary operators of n bits is reconfigured into two ternary logic operators having the same input each time, and reconfiguration is performed three times for implementation; each of ternary operators of n bits is reconfigured into five ternary logic operators of the same time, and reconfiguration is performed once for implementation; corresponding unreconfigurable ternary logic operators are used instead for the foregoing reconfiguration process.

An embodiment method of processing at least one sensing signal comprising a time-series of signal samples comprises high-pass filtering the time series of signal samples to produce a filtered time series; applying delay embedding processing to the filtered time series; producing a first matrix by storing the set of time-shifted time series as an ordered list of entries in the first matrix; applying a first truncation to produce a second matrix by truncating the entries in the ordered list of entries at one end of the first matrix to remove a number of items equal to the product of the first delay embedding parameter decreased by one times the second delay embedding parameter; applying entry-wise processing to the second matrix, and forwarding a set of estimated kernel densities and/or a set of images generated as a function of the set of estimated kernel densities to a user circuit.

Embodiments of the present disclosure are directed toward techniques and configurations for an optical accelerator including a photonics integrated circuit (PIC) for an optical neural network (ONN). In embodiments, an optical accelerator package includes the PIC and an electronics integrated circuit (EIC) that is heterogeneously integrated into the optical accelerator package to proximally provide pre- and post-processing of optical signal inputs and optical signal outputs provided to and received from an optical matrix multiplier of the PIC. In some embodiments, the EIC is a single EIC or discrete EICs to provide pre- and post-processing of the optical signal inputs and optical signal outputs including optical to electrical and electrical to optical transduction. Other embodiments may be described and/or claimed.

A system for parallel photonic computation, preferably including one or more source modules, a plurality of multiplication modules, and a plurality of summation modules. In one embodiment, each multiplication module can include a set of input modulators, a splitter, and a plurality of multiplication banks. Each summation module can include one or more detectors. Each summation module preferably receives an output from multiple multiplication modules and computes the sum of all channels of all the received outputs. A method for parallel photonic computation, preferably including generating input signals, computing products, and computing sums.

A system for parallel photonic computation, preferably including one or more source modules, a plurality of multiplication modules, and a plurality of summation modules. In one embodiment, each multiplication module can include a set of input modulators, a splitter, and a plurality of multiplication banks. Each summation module can include one or more detectors. Each summation module preferably receives an output from multiple multiplication modules and computes the sum of all channels of all the received outputs. A method for parallel photonic computation, preferably including generating input signals, computing products, and computing sums.