Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.

A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.

The invention relates to a device for generating a plurality of clock signals or high-frequency signals. The devices includes a reference signal generator, which is connected to an oscillator and generates at its output a reference signal with a reference frequency fx. The device also includes at least one signal processor, for example, a DDS, which is connected to the reference frequency generator via a first signal line and to which the reference signal with the reference frequency fx is supplied, and which is configured to generate an output signal having a frequency less than fx.

The invention relates to a device for generating a plurality of clock signals or high-frequency signals. The devices includes a reference signal generator, which is connected to an oscillator and generates at its output a reference signal with a reference frequency fx. The device also includes at least one signal processor, for example, a DDS, which is connected to the reference frequency generator via a first signal line and to which the reference signal with the reference frequency fx is supplied, and which is configured to generate an output signal having a frequency less than fx.

For calculating load resistance, a pulse generation module drives a pulse width modulation (PWM) inverter in response to a control voltage. The PWM inverter includes a U phase pole, a V phase pole, and a W phase pole. Each U, V, and W phase pole includes an upper pole device and a lower pole device. The PWM inverter turns off the U phase pole, turns on the W upper pole device, turns off the W lower pole device, and applies the control voltage to the V upper pole device and the V lower pole device. A forward drop correction module corrects the control voltage based on a feedforward compensation voltage determined from a forward voltage drop. A load resistance module calculates a load resistance for a load based on an average control voltage, an average bus voltage, and an average load feedback current.

For calculating load resistance, a pulse generation module drives a pulse width modulation (PWM) inverter in response to a control voltage. The PWM inverter includes a U phase pole, a V phase pole, and a W phase pole. Each U, V, and W phase pole includes an upper pole device and a lower pole device. The PWM inverter turns off the U phase pole, turns on the W upper pole device, turns off the W lower pole device, and applies the control voltage to the V upper pole device and the V lower pole device. A forward drop correction module corrects the control voltage based on a feedforward compensation voltage determined from a forward voltage drop. A load resistance module calculates a load resistance for a load based on an average control voltage, an average bus voltage, and an average load feedback current.

The kernel function generation unit 81 defines a first kernel function by using two-dimensional feature representation that represents a combination of two features of data. The model learning unit 82 defines a linear model including an inner product of a mapping used in the first kernel function and a first weight and performs learning with the defined linear model. The component expanding unit 83 expands the learned linear model to define expanded component representation that is new component representation of the data. The expansion model generation unit 84 generates an expansion model including an inner product of data by the expanded component representation and a second weight.

The kernel function generation unit 81 defines a first kernel function by using two-dimensional feature representation that represents a combination of two features of data. The model learning unit 82 defines a linear model including an inner product of a mapping used in the first kernel function and a first weight and performs learning with the defined linear model. The component expanding unit 83 expands the learned linear model to define expanded component representation that is new component representation of the data. The expansion model generation unit 84 generates an expansion model including an inner product of data by the expanded component representation and a second weight.