A method for coding information of a point cloud comprises obtaining the point cloud including a set of points in a three-dimensional space; partitioning the point cloud into a plurality of objects and generating occupancy information for each of the plurality of objects; and encoding the occupancy information by taking into account the distance between the plurality of objects.

A logic circuit comprising: inputs for receiving multiple n-bit numbers, n being greater than one; and an adder capable of receiving m n-bit numbers, m being greater than one, and forming an output representing the sum of those numbers, the adder having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the numbers to an operation in a respective one of the single-bit stages, the single-bit stages being such that the adder has insufficient capacity to add all possible combinations of bits in a respective bit position of m n-bit numbers; the addition circuit being configured to add the multiple n-bit numbers by: in the adder, adding a first one of the n-bit numbers to a value corresponding to a set of non-consecutive bits of another of the n-bit numbers to form a first intermediate value; adding the first intermediate value to a value corresponding to the bits of the said other of the n-bit numbers other than those in the said set to form a sum; and outputting the sum.

A logic circuit comprising: inputs for receiving multiple n-bit numbers, n being greater than one; and an adder capable of receiving m n-bit numbers, m being greater than one, and forming an output representing the sum of those numbers, the adder having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the numbers to an operation in a respective one of the single-bit stages, the single-bit stages being such that the adder has insufficient capacity to add all possible combinations of bits in a respective bit position of m n-bit numbers; the addition circuit being configured to add the multiple n-bit numbers by: in the adder, adding a first one of the n-bit numbers to a value corresponding to a set of non-consecutive bits of another of the n-bit numbers to form a first intermediate value; adding the first intermediate value to a value corresponding to the bits of the said other of the n-bit numbers other than those in the said set to form a sum; and outputting the sum.

A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.

A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.

An execution unit comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions. The processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result. Each of a plurality of processing circuits in the pipeline is configured to perform an operation on input values during at least one stage of the plurality of stages. The plurality of processing circuits include multiplier circuits. A first multiplier circuit and a second multiplier circuit are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform their processing. A third multiplier circuit is arranged in series with the first multiplier circuit and the second multiplier circuit and processes outputs from the first multiplier circuit and the second multiplier circuit.

An execution unit comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions. The processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result. Each of a plurality of processing circuits in the pipeline is configured to perform an operation on input values during at least one stage of the plurality of stages. The plurality of processing circuits include multiplier circuits. A first multiplier circuit and a second multiplier circuit are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform their processing. A third multiplier circuit is arranged in series with the first multiplier circuit and the second multiplier circuit and processes outputs from the first multiplier circuit and the second multiplier circuit.

The present disclosure relates to a method and an apparatus for approximating non-linear function. In some embodiments, an exemplary processing unit includes: one or more registers for storing a lookup table (LUT) and one or more operation elements communicatively coupled with the one or more registers. The LUT includes a control state and a plurality of data entries. The one or more operation elements are configured to: receive an input operand; select one or more bits from the input operand; select a data entry from the plurality of data entries using the one or more bits; and determine an approximation value of a non-linear activation function for the input operand using the data entry.