A low power sensing device includes a sensor including key sensors configured to generate sensing signals, respectively, a reference sensor configured to generate a reference sensing signal, a two-state clock generator configured to generate a first clock signal and a second clock signal having clock frequencies different from each other, and a controller. The controller is configured to receive the sensing signals and the reference sensing signal, control enable operations and disable operations of the sensor and the reference sensor based on a first operation mode and a second operation mode each repeatedly performed for a predetermined time, receive the first clock signal during the first operation mode, and receive the second clock signal during the second operation mode.

A method and system to provide timebase synchronization for multiple processors in a multi-processor sensor system, where each processor operates according to a respective reference clock, and where the processors' respective reference clocks are off sync from each other. An example method includes simultaneously injecting a synchronization pulse respectively into the multiple processors. Further, the method includes recording for each processor, according to the processor's respective reference clock, a respective synchronization-pulse timestamp of the simultaneously injected synchronization pulse, comparing the respective synchronization-pulse timestamps recorded for the processors, and, based on the comparing, computing for each processor a respective time offset. Additionally, the method includes using the per-processor computed time offsets as a basis to provide a synchronized timebase across the processors.

A method and system to provide timebase synchronization for multiple processors in a multi-processor sensor system, where each processor operates according to a respective reference clock, and where the processors' respective reference clocks are off sync from each other. An example method includes simultaneously injecting a synchronization pulse respectively into the multiple processors. Further, the method includes recording for each processor, according to the processor's respective reference clock, a respective synchronization-pulse timestamp of the simultaneously injected synchronization pulse, comparing the respective synchronization-pulse timestamps recorded for the processors, and, based on the comparing, computing for each processor a respective time offset. Additionally, the method includes using the per-processor computed time offsets as a basis to provide a synchronized timebase across the processors.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

Systems and methods include techniques for recording information for tracing a timestamp to its source. The techniques can facilitate auditing of a time service by external auditors. The timestamps can be collected from all the sources and intermediate touch points like timing and network switches and can be stored in a distributed time ledger. In one example, a method includes receiving, at a collection time by a time collector, a timestamp from each of a plurality of timing devices at a collection time; aggregating the timestamp of each of the plurality of timing devices into a timestamp record, the timestamp record including the collection time and a timestamp entry for each of the timing devices, wherein the timestamp entry for a timing device includes a timing device identifier and the timestamp corresponding to the timing device providing the timestamp; and inserting the timestamp record into an immutable time ledger.

Systems and methods include techniques for recording information for tracing a timestamp to its source. The techniques can facilitate auditing of a time service by external auditors. The timestamps can be collected from all the sources and intermediate touch points like timing and network switches and can be stored in a distributed time ledger. In one example, a method includes receiving, at a collection time by a time collector, a timestamp from each of a plurality of timing devices at a collection time; aggregating the timestamp of each of the plurality of timing devices into a timestamp record, the timestamp record including the collection time and a timestamp entry for each of the timing devices, wherein the timestamp entry for a timing device includes a timing device identifier and the timestamp corresponding to the timing device providing the timestamp; and inserting the timestamp record into an immutable time ledger.

The present disclosure relates to digital signal processing architectures, and more particularly to a modular object-oriented digital system architecture ideally suited for radar, sonar and other general purpose instrumentation which includes the ability to self-discover modular system components, self-build internal firmware and software based on the modular components, sequence signal timing across the modules and synchronize signal paths through multiple system modules.

The present disclosure relates to digital signal processing architectures, and more particularly to a modular object-oriented digital system architecture ideally suited for radar, sonar and other general purpose instrumentation which includes the ability to self-discover modular system components, self-build internal firmware and software based on the modular components, sequence signal timing across the modules and synchronize signal paths through multiple system modules.

An electrical circuit, having: an oscillating element configured to provide a clock signal; and a clock synchronization unit configured to adapt the clock signal based on a reference signal; wherein the clock synchronization unit is configured to extract from an alternating signal the reference signal.