Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.

Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

Systems and methods for improving power efficiency of electronic systems are disclosed. An intelligent voltage regulator module (VRM) can self-regulate the output power provided to one or more components of an electronic system. For example, output voltage to a component can be increased when more computational power is needed or lowered when appropriate. The intelligent VRM can regulate the output power, for instance, based on one or more of usage or activity of the component. In some cases, the intelligent VRM can independently regulate the output power without input from a host device or override one or more output power parameters. Adjustment of the output power can be performed using machine learning (ML).

Systems and methods for improving power efficiency of electronic systems are disclosed. An intelligent voltage regulator module (VRM) can self-regulate the output power provided to one or more components of an electronic system. For example, output voltage to a component can be increased when more computational power is needed or lowered when appropriate. The intelligent VRM can regulate the output power, for instance, based on one or more of usage or activity of the component. In some cases, the intelligent VRM can independently regulate the output power without input from a host device or override one or more output power parameters. Adjustment of the output power can be performed using machine learning (ML).

An apparatus comprises a first power supply, a second power supply, and a controller. The first power supply supplies a first input voltage to power a first input of a load over a first circuit path. The second power supply supplies a second input voltage to power a second input of the load over a second circuit path. The controller controls connectivity of the first circuit path to the second circuit path as a function of the first input voltage and the second input voltage during at least ramp up or ramp down of either or both of the first input voltage and the second input voltage.

An apparatus comprises a first power supply, a second power supply, and a controller. The first power supply supplies a first input voltage to power a first input of a load over a first circuit path. The second power supply supplies a second input voltage to power a second input of the load over a second circuit path. The controller controls connectivity of the first circuit path to the second circuit path as a function of the first input voltage and the second input voltage during at least ramp up or ramp down of either or both of the first input voltage and the second input voltage.