A memory card controller coupled to a host device includes a processing circuit which is used for reading card specific data from a flash memory of a memory card to store the card specific data in a register wherein a multiply parameter and a basic capacity are marked in the card specific data and used for sending the card specific data to the host device to make the host device calculate a maximum capacity of the memory card according to the multiply parameter and the basic capacity marked in the card specific data.

This storage system has one or more non-volatile memory devices and a processor unit that comprises one or more processors connected to the one or more non-volatile memory devices. At least a portion of the non-volatile memory of each of the one or more non-volatile memory devices comprises a user area, which is a storage area to which data is written, and an update area, which is a storage area to which update data for the original data is written. The processor unit changes the user capacity, namely the capacity of the user area, of each of the one or more non-volatile memory devices on the basis of at least one of one or more resource usage rates of the one or more non-volatile memory devices.

This storage system has one or more non-volatile memory devices and a processor unit that comprises one or more processors connected to the one or more non-volatile memory devices. At least a portion of the non-volatile memory of each of the one or more non-volatile memory devices comprises a user area, which is a storage area to which data is written, and an update area, which is a storage area to which update data for the original data is written. The processor unit changes the user capacity, namely the capacity of the user area, of each of the one or more non-volatile memory devices on the basis of at least one of one or more resource usage rates of the one or more non-volatile memory devices.

A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.

A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.

A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

A time display device, including: an indication display unit which displays a content according to an indicating operation, and a processor, wherein in a case where a remaining time with respect to a reference set time of an elapsed time from a measuring start timing is greater than a predetermined reference remaining time, the processor makes the indication display unit display a ratio of the remaining time with respect to the reference set time, and in a case where the remaining time is equal to or less than the predetermined reference remaining time, the processor makes the indication display unit display the remaining time.

Machine learning may include training and drawing inference from artificial neural networks, processes which may include performing convolution and matrix multiplication operations. Convolution and matrix multiplication operations are performed using vectors of block floating-point (BFP) values that may include outliers. BFP format stores floating-point values using a plurality of mantissas of a fixed bit width and a shared exponent. Elements are outliers when they are too large to be represented precisely with the fixed bit width mantissa and shared exponent. Outlier values are split into two mantissas. One mantissa is stored in the vector with non-outliers, while the other mantissa is stored outside the vector. Operations, such as a dot product, may be performed on the vectors in part by combining the in-vector mantissa and exponent of an outlier value with the out-of-vector mantissa and exponent.

Machine learning may include training and drawing inference from artificial neural networks, processes which may include performing convolution and matrix multiplication operations. Convolution and matrix multiplication operations are performed using vectors of block floating-point (BFP) values that may include outliers. BFP format stores floating-point values using a plurality of mantissas of a fixed bit width and a shared exponent. Elements are outliers when they are too large to be represented precisely with the fixed bit width mantissa and shared exponent. Outlier values are split into two mantissas. One mantissa is stored in the vector with non-outliers, while the other mantissa is stored outside the vector. Operations, such as a dot product, may be performed on the vectors in part by combining the in-vector mantissa and exponent of an outlier value with the out-of-vector mantissa and exponent.

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.